參數(shù)資料
型號(hào)： ADSP-21MSP5859
廠(chǎng)商： Analog Devices, Inc.
英文描述： LM101A/LM201A/LM301A Operational Amplifiers; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail
中文描述： DSP的微機(jī)
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 231K
代理商： ADSP-21MSP5859
ADSP-21mod870
–12–
REV. 0
Figure 9 shows the IDMA Control and OVLAY Registers, Fig-
ure 10 shows the bus usage during IDMA transfers, and Figure
11 shows the DMA memory maps.
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
9
DM(0x3FE0)
IDMAA
ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
IDMA OVERLAY
9
8
DM(0x3FE7)
RESERVED
SET TO 0
ID DMOVLAY
ID PMOVLAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
8
7
6
5
4
3
2
1
0
Figure 9. IDMA Control/OVLAY Registers
(IAD 15–0)
8
0 = PM
1 = DM
1
0
0
0
0
0
0
0
DM PAGE
PM PAGE
15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
PAGE
LATCH
ADDRESS
LATCH
0
ADDRESS
PAGE AND ADDRESS LATCH
(IAD 15–0)
8
DATA
LOWER BYTE
15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
DM 16-BIT
IDMA DATA WRITE/INPUT
DATA
UPPER BYTE
DATA
MIDDLE BYTE
PM 24-BIT
DATA
UPPER BYTE
DATA
LOWER BYTE
IGNORED
1ST
TRANSFER
2ND
TRANSFER
(IAD 15–0)
8
DATA
LOWER BYTE
15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
DM 16-BIT
IDMA DATA READ/OUTPUT
DATA
UPPER BYTE
DATA
MIDDLE BYTE
PM 24-BIT
DATA
UPPER BYTE
DATA
LOWER BYTE
0
0
0
0
0
0
0
0
1ST
TRANSFER
2ND
TRANSFER
Figure 10. Bus Usage During IDMA Transfers
ACCESSIBLE WHEN
PMOVLAY = 5
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
ACCESSIBLE WHEN
0x2000–
0x3FFF
0x2000–
0x3FFF
0x2000–
0x3FFF
PROGOVLAY
NOTE:
IDMA AND BDMA HAVE
ACCESSIBLE WHEN
DMOVLAY = 5
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
ACCESSIBLE WHEN
0x0000–
0x1FFF
0x0000–
0x1FFF
0x0000–
0x1FFF
DATOVLAY
Figure 11. Direct Memory Access-PM and DM Memory
Maps
Bootstrap Loading (Booting)
The ADSP-21mod870 has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.
When the MODE pins specify BDMA booting, the ADSP-
21mod870 initiates a BDMA boot sequence when reset is
released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at Address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate boot code compatible with byte memory space.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-21mod870. The only memory address bit provided by
the processor is A0.
IDMA Port Booting
The ADSP-21mod870 can also boot programs through its In-
ternal DMA port. If Mode C = 1, Mode B = 0, and Mode A =
1, the ADSP-21mod870 boots from the IDMA port. IDMA
feature can load as much on-chip memory as desired. Program
execution is held off until data is written to on-chip program
memory location 0.
Bus Request and Bus Grant
The ADSP-21mod870 can relinquish control of the data and
address buses to an external device. When the external device
requires access to memory, it asserts the bus request (
BR
)
signal. If the ADSP-21mod870 is not performing an external
memory access, it responds to the active
BR
input in the follow-
ing processor cycle by:
Three-stating the data and address buses and the
PMS
,
DMS
,
BMS
,
CMS
,
IOMS
,
RD
,
WR
output drivers,
Asserting the bus grant (
BG
) signal and
Halting program execution.
If Go Mode is enabled, the ADSP-21mod870 will not halt pro-
gram execution until it encounters an instruction that requires an
external memory access.
If the ADSP-21mod870 is performing an external memory access
when the external device asserts the
BR
signal, it will not three-
state the memory interfaces or assert the
BG
signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
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