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參數(shù)資料
| 型號： | ADSP-21MOD870 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Internet Gateway Processor |
| 中文描述： | 互聯(lián)網(wǎng)網(wǎng)關(guān)處理器 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ADSP-21MOD870 |
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ADSP-21mod870
–4–
REV. 0
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-21mod870 provides up to 13 general-purpose flag
pins. The data input and output pins on SPORT1 can be alter-
natively configured as an input flag and an output flag. In addi-
tion, there are eight flags that are programmable as inputs or
outputs, and three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every
n
processor
cycles, where
n
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-21mod870 incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-21mod870
SPORTs. For additional information on Serial Ports, refer to the
ADSP-2100 Family User’s Manual, Third Edition
.
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
μ
-law companding according
to CCITT recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORTs can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An interrupt is
generated after a data buffer transfer.
SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
SPORT1 can be configured to have two external interrupts
(
IRQ0
and
IRQ1
) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
The ADSP-21mod870 is available in a 100-lead LQFP package.
To maintain maximum functionality and reduce package size
and pin count, some serial port, programmable flag, interrupt,
and external bus pins have dual, multiplexed functionality. The
external bus pins are configured during RESET, while serial
port pins are software configurable during program execution.
Flag and interrupt functionality is retained concurrently on
multiplexed pins. The following table shows the common-mode
pins. When pin functionality is configurable, the default state is
shown in plain text, alternate functionality is in italics.
Common-Mode Pins
#
of
Pins put
1
1
1
1
1
1
1
1
1
1
1
1
Input/
Out-
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive
Interrupt Request
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port 0 Pins (
TFS0
,
RFS0
,
DT0
,
DR0
,
SCLK0
)
Serial Port 1 Pins (
TFS1
,
RFS1
,
DT1
,
DR1
,
SCLK1
)
I
I
O
O
O
O
O
O
O
O
O
I
PF7
IRQL1/
PF6
IRQL0/
PF5
IRQE/
PF4
Mode D/
I/O
I
I/O
I
I/O
I
I/O
I
1
1
1
1
PF3
I/O
Mode C/
1
I
PF2
I/O
Mode B/
1
I
PF1
I/O
Mode A/
1
I
PF0
I/O
CLKIN, XTAL
CLKOUT
SPORT0
2
1
5
I
O
I/O
SPORT1
2
5
I/O
or
Interrupts and Flags:
IRQ0
(
RFS1
)
IRQ1
(
TFS1
)
FI (
DR1
)
FO (
DT1
)
PWD
PWDACK
FL0, FL1, FL2
V
DD
and GND
EZ-Port
1
1
1
1
1
1
3
16
9
I
I
I
O
I
O
O
I
I/O
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
Power-Down Control Input
Power-Down Control Output
Output Flags
Power and Ground
For Emulation Use
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the
corresponding interrupts, the DSP will vector to the appropriate interrupt vector address
when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software
configurable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21MOD870-000 | Internet Gateway Processor |
| ADSP-21XX1111 | ADSP-2100 Family DSP Microcomputers |
| ADSP-21XX4444 | ADSP-2100 Family DSP Microcomputers |
| ADSP-21MSP5859 | LM101A/LM201A/LM301A Operational Amplifiers; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail |
| ADSP-21XX | ADSP-2100 Family DSP Microcomputers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MOD870-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD880-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD880NB000 | 制造商:Analog Devices 功能描述: |
| ADSP-21MOD885-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
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