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參數(shù)資料
| 型號： | ADSP-21MOD870 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Internet Gateway Processor |
| 中文描述： | 互聯(lián)網(wǎng)網(wǎng)關(guān)處理器 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ADSP-21MOD870 |
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ADSP-21mod870
–13–
REV. 0
When the
BR
signal is released, the processor releases the
BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when
RESET
is active.
The
BGH
pin is asserted when the ADSP-21mod870 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-21mod870 deasserts
BG
and
BGH
and executes the
external memory access.
Flag I/O Pins
The ADSP-21mod870 has eight general purpose programmable
input/output flag pins. They are controlled by two memory map-
ped registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-21mod870’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-21mod870
has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1,
and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
Instruction Set Description
The ADSP-21mod870 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following ben-
efits:
The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
21mod870’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod870 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-
pin plug. See the
ADSP-2100 Family EZ-Tools
data sheet for
complete information on ICE products.
Issuing the “chip reset” command during emulation causes the
DSP processor to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are set
correctly PRIOR to issuing a chip reset command from the emu-
lator user interface. As the mode pins share functionality with
PF0:2 (and PF3 on the ADSP-21mod870), it may be necessary
to reset the target hardware separately to insure the proper mode
selection state on emulator chip reset.
If you are using a passive method of maintaining mode informa-
tion (as discussed in the Setting Memory Modes section), it
does not matter that mode information is latched by an emula-
tor reset. However, if you are using the
RESET
pin as a method
of setting the value of the mode pins, then you must consider
the effects of an emulator reset.
One method of ensuring that the values located on the mode
pins is correct is to construct a circuit like the one shown below.
This circuit will force the value located on the mode A pin
to zero, regardless of whether it latched via the
RESET
or
ERESET
pin.
ERESET
RESET
MODE A/PFO
PROGRAMMABLE I/O
1k
V
Figure 12.
RESET
,
ERESET
Circuit
See the
ADSP-2100 Family EZ-Tools
data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-21mod870
pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
These ADSP-21mod870 pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
21mod870 and the connector must be kept as short as possible,
no longer that three inches.
The following pins are also used by the EZ-ICE:
BR
RESET
BG
GND
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-21mod870 in the target system. This causes the
processor to use its
ERESET
,
EBR
and
EBG
pins instead of the
RESET
,
BR
and
BG
pins. The
BG
output is three-stated. These
signals do not need to be jumper-isolated in your system.
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PDF描述 |
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| ADSP-21MOD870-000 | Internet Gateway Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MOD870-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD880-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD880NB000 | 制造商:Analog Devices 功能描述: |
| ADSP-21MOD885-000 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
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