參數(shù)資料
型號: ADSP-21990BST
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 16-bit fixed point DSP with Flash
中文描述: 16-BIT, 160 MHz, OTHER DSP, PQFP176
封裝: MS-026BGA, LQFP-176
文件頁數(shù): 11/44頁
文件大?。?/td> 574K
代理商: ADSP-21990BST
–11–
REV. 0
ADSP-21990
Peripheral Interrupt Controller
The Peripheral Interrupt Controller is a dedicated peripheral unit
of the ADSP-21990 (accessed via IO mapped registers). The
peripheral interrupt controller manages the connection of up to
32 peripheral interrupt requests to the DSP core.
For each peripheral interrupt source, there is a unique 4-bit code
that allows the user to assign the particular peripheral interrupt
to any one of the 12 user assignable interrupts of the embedded
ADSP-219x core. Therefore, the peripheral interrupt controller
of the ADSP-21990 contains eight, 16-bit Interrupt Priority
Registers (Interrupt Priority Register 0 (IPR0) to Interrupt
Priority Register 7 (IPR7)).
Each Interrupt Priority Register contains a four 4-bit codes; one
specifically assigned to each peripheral interrupt. The user may
write a value between 0x0 and 0xB to each 4-bit location in order
to effectively connect the particular interrupt source to the cor-
responding user assignable interrupt of the ADSP-219x core.
Writing a value of 0x0 connects the peripheral interrupt to the
USR0 user assignable interrupt of the ADSP-219x core while
writing a value of 0xB connects the peripheral interrupt to the
USR11 user assignable interrupt. The core interrupt USR0 is the
highest priority user interrupt, while USR11 is the lowest priority.
Writing a value between 0xC and 0xF effectively disables the
peripheral interrupt by not connecting it to any ADSP-219x core
interrupt input. The user may assign more than one peripheral
interrupt to any given ADSP-219x core interrupt. In that case,
the burden is on the user software in the interrupt vector table to
determine the exact interrupt source through reading status bits.
This scheme permits the user to assign the number of specific
interrupts that are unique to their application to the interrupt
scheme of the ADSP-219x core. The user can then use the
existing interrupt priority control scheme to dynamically control
the priorities of the 12 core interrupts.
Low Power Operation
The ADSP-21990 has four low power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-21990 uses the con-
figuration of the PD, STCK, and STALL bits in the PLLCTL
register to select between the low power modes as the DSP
executes the IDLE instruction. Depending on the mode, an
IDLE shuts off clocks to different parts of the DSP in the different
modes. The low power modes are:
Idle
Power-Down Core
Power-Down Core/Peripherals
Power-Down All
Idle Mode
When the ADSP-21990 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core Mode
When the ADSP-21990 is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core/Peripherals Mode
When the ADSP-21990 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
Table 2. Interrupt Priorities/Addresses
Interrupt
IMASK/
IRPTL
Vector Address
Emulator (NMI)
—Highest Priority
Reset (NMI)
Power Down (NMI)
Loop and PC Stack
Emulation Kernel
User Assigned Interrupt
(USR0)
User Assigned Interrupt
(USR1)
User Assigned Interrupt
(USR2)
User Assigned Interrupt
(USR3)
User Assigned Interrupt
(USR4)
User Assigned Interrupt
(USR5)
User Assigned Interrupt
(USR6)
User Assigned Interrupt
(USR7)
User Assigned Interrupt
(USR8)
User Assigned Interrupt
(USR9)
User Assigned Interrupt
(USR10)
User Assigned Interrupt
(USR11)
—Lowest Priority
NA
NA
0
1
2
3
4
0x00 0000
0x00 0020
0x00 0040
0x00 0060
0x00 0080
5
0x00 00A0
6
0x00 00C0
7
0x00 00E0
8
0x00 0100
9
0x00 0120
10
0x00 0140
11
0x00 0160
12
0x00 0180
13
0x00 01A0
14
0x00 01C0
15
0x00 01E0
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