參數(shù)資料
型號(hào)： ADSP-2191MKCA-160
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SPI，SSP，UART
時(shí)鐘速率： 160MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 3.00V，3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤
ADSP-2191M
–10–
REV. A
Ten memory-mapped registers control operation of the Program-
mable Flag pins:
Flag Direction register
Specifies the direction of each individual PFx pin as input
or output.
Flag Control and Status registers
Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.
Flag Interrupt Mask registers
Enable and disable each individual PFx pin to function
as an interrupt to the DSP’s core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts—latching in the IMASK and IRPTL
registers.
Flag Interrupt Polarity register
Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin.
Flag Sensitivity registers
Specify whether individual PFx pins are level- or
edge-sensitive and specify—if edge-sensitive—whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif-
icant for edge-sensitivity.
Low Power Operation
The ADSP-2191M has four low power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-2191M uses configu-
ration of the PDWN, STOPCK, and STOPALL bits in the
PLLCTL register to select between the low power modes as the
DSP executes the IDLE. Depending on the mode, an IDLE shuts
off clocks to different parts of the DSP in the different modes.
The low power modes are:
Idle
Power-Down Core
Power-Down Core/Peripherals
Power-Down All
Idle Mode
When the ADSP-2191M is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core Mode
When the ADSP-2191M is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To enter Power-Down Core mode, the DSP executes an IDLE
instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Clear (= 0) the PDWN bit in the PLLCTL register
Clear (= 0) the STOPALL bit in the PLLCTL register
Set (= 1) the STOPCK bit in the PLLCTL register
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core/Peripherals Mode
When the ADSP-2191M is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
To enter Power-Down Core/Peripherals mode, the DSP executes
an IDLE instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Clear (= 0) the PDWN bit in the PLLCTL register
Set (= 1) the STOPALL bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP responds
to a wake-up event and (after five to six cycles of latency) resumes
executing instructions with the instruction after the IDLE.
Power-Down All Mode
When the ADSP-2191M is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Set (= 1) the PDWN bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after
the IDLE.
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