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參數(shù)資料
| 型號： | ADSP-2188MKSTZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. 0
ADSP-2188M
–11–
RESET
The
RESET signal initiates a master reset of the ADSP-2188M.
The
RESET signal must be asserted during the power-up
sequence to assure proper initialization.
RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for the
crystal oscillator circuit to stabilize after a valid VDD is applied to
the processor, and for the internal phase-locked loop (PLL) to lock
onto the specific crystal frequency. A minimum of 2000 CLKIN
cycles ensures that the PLL has locked but does not include the
crystal oscillator start-up time. During this power-up sequence
the
RESET signal should be held low. On any subsequent resets,
the
RESET signal must meet the minimum pulsewidth specifi-
cation, tRSP.
The
RESET input contains some hysteresis; however, if an
RC circuit is used to generate the
RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and clears the MSTAT register.
When
RESET is released, if there is no pending bus request and
the chip is configured for booting, the boot-loading sequence is
performed. The first instruction is fetched from on-chip pro-
gram memory location 0x0000 once boot loading completes.
Power Supplies
The ADSP-2188M has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.75 V requirement. The
external supply can be connected to either a 2.75 V or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up to
Table II. Modes of Operation
MODE D
MODE C
MODE B
MODE A
Booting Method
X
0
BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Full Memory Mode.
1
X
010No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used, but the processor does not automatically use or wait for these
operations.
0100
BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Host Mode.
IACK has active
pull-down. (REQUIRES ADDITIONAL HARDWARE).
0101IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written
to. Chip is configured in Host Mode.
IACK has active pull-down.1
1100
BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Host Mode;
IACK requires exter-
nal pull down. (REQUIRES ADDITIONAL HARDWARE)
1101IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written
to. Chip is configured in Host Mode.
IACK requires external pull-down.1
NOTE
1Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
3.6 V, regardless of the external supply voltage. This feature pro-
vides maximum flexibility in mixing 2.75 V and 3.3 V components.
MODES OF OPERATION
Setting Memory Mode
Memory Mode selection for the ADSP-2188M is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive Configuration
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power con-
sumption, or if the PF2 pin is to be used as an output in the DSP
application, a weak pull-up or pull-down, on the order of 10 k
,
can be used. This value should be sufficient to pull the pin to the
desired level and still allow the pin to operate as a programmable
flag output without undue strain on the processor’s output driver.
For minimum power consumption during power-down, recon-
figure PF2 to be an input, as the pull-up or pull-down will
hold the pin in a known state, and will not switch.
Active Configuration
Active Configuration involves the use of a three-statable external
driver connected to the Mode C pin. A driver’s output enable
should be connected to the DSP’s
RESET signal such that it
only drives the PF2 pin when
RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
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