參數(shù)資料
型號: ADSP-2187NBCA-320
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 24-BIT, 40 MHz, OTHER DSP, PBGA144
封裝: MO-205AC, BGA-144
文件頁數(shù): 19/48頁
文件大?。?/td> 1571K
代理商: ADSP-2187NBCA-320
–19–
REV. 0
ADSP-218xN Series
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and
FL2. FL0–FL2 are dedicated output flags. FI and FO are
available as an alternate configuration of SPORT1.
Note:
Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The ADSP-218xN series assembly language instruction set
has an algebraic syntax that was designed for ease of coding
and readability. The assembly language, which takes full
advantage of the processor’s unique architecture, offers the
following benefits:
The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly
language and is completely source and object code com-
patible with other family members. Programs may need
to be relocated to utilize on-chip memory and conform to
the ADSP-218xN’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the
condition can be checked and the operation executed in
the same instruction cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruc-
tion cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
ADSP-218xN series members have on-chip emulation
support and an ICE-Port, a special set of pins that interface
to the EZ-ICE. These features allow in-circuit emulation
without replacing the target system processor by using only
a 14-pin connection from the target system to the EZ-ICE.
Target systems must have a 14-pin connector to accept the
EZ-ICE’s in-circuit probe, a 14-pin plug.
Note:
The EZ-ICE uses the same V
DD
voltage as the V
DD
voltage used for V
DDEXT
. Because the input pins of the
ADSP-218xN series members are tolerant to input voltages
up to 3.6 V, regardless of the value of V
DDEXT
, the voltage
setting for the EZ-ICE must not exceed 3.3 V.
Issuing the chip reset command during emulation causes
the DSP to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are
set correctly PRIOR to issuing a chip reset command from
the emulator user interface. If a passive method of maintain-
ing mode information is being used (as discussed in
Setting
Memory Mode on page 11
), it does not matter that the
mode information is latched by an emulator reset. However,
if the RESET pin is being used as a method of setting the
value of the mode pins, the effects of an emulator reset must
be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one
shown in
Figure 14
. This circuit forces the value located on
the Mode A pin to logic high, regardless of whether it is
latched via the RESET or ERESET pin.
The ICE-Port interface consists of the following ADSP-
218xN pins: EBR, EINT, EE, EBG, ECLK, ERESET,
ELIN, EMS, and ELOUT.
These ADSP-218xN pins must be connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-
up or pull-down resistors. The traces for these signals
between the ADSP-218xN and the connector must be kept
as short as possible, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-218xN in the target system. This
causes the processor to use its ERESET, EBR, and EBG
pins instead of the RESET, BR, and BG pins. The BG
output is three-stated. These signals do not need to be
jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto
the 14-pin connector (a pin strip header) on the target
board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is
shown in
Figure 15
. This connector must be added to the
target board design to use the EZ-ICE. Be sure to allow
enough room in the system to fit the EZ-ICE probe onto
the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7
location—Pin 7 must be removed from the header. The pins
must be 0.025 inch square and at least 0.20 inch in length.
Figure 14. Mode A Pin/EZ-ICE Circuit
PROGRAMMABLE I/O
MODE A/PF0
RESET
ERESET
ADSP-218xN
1k
相關(guān)PDF資料
PDF描述
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ADSP-2187NKCA-320 DSP Microcomputer
ADSP-2187NKST-320 DSP Microcomputer
ADSP-2188NKCA-320 DSP Microcomputer
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