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參數(shù)資料
| 型號： | ADSP-2187NBCA-320 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 40 MHz, OTHER DSP, PBGA144 |
| 封裝： | MO-205AC, BGA-144 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | ADSP-2187NBCA-320 |
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–15–
REV. 0
ADSP-218xN Series
Memory-Mapped Registers (New to the ADSP-218xM
and N series)
ADSP-218xN series members have three memory-mapped
registers that differ from other ADSP-21xx Family DSPs.
The slight modifications to these registers (Wait State Con-
trol, Programmable Flag and Composite Select Control,
and System Control) provide the ADSP-218xN’s wait state
and BMS control features. Default bit values at reset are
shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a grey field. These bits should
always be written with zeros.
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional exter-
nal memory space called I/O space. This space is designed
to support simple connections to peripherals (such as data
converters and external registers) or to bus interface ASIC
data registers. I/O space supports 2048 locations of 16-bit
wide data. The lower eleven bits of the external address bus
are used; the upper three bits are undefined.
Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait
state registers, IOWAIT0–3 as shown in
Figure 9
, which in
combination with the wait state mode bit, specify up to 15
wait states to be automatically generated for each of four
regions. The wait states act on address ranges, as shown
in
Table 10
.
Note
: In Full Memory Mode, all 2048 locations of I/O space
are directly addressable. In Host Memory Mode, only
address pin A0 is available; therefore, additional logic is
required externally to achieve complete addressability of the
2048 I/O space locations.
Composite Memory Select
ADSP-218xN series members have a programmable
memory select signal that is useful for generating memory
select signals for memories mapped to more than one space.
The CMS signal is generated to have the same timing as
each of the individual memory select signals (PMS, DMS,
BMS, IOMS) but can combine their functionality. Each bit
in the CMSSEL register, when set, causes the CMS signal
to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in
the CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable
bit causes the assertion of the CMS signal at the same time
as the selected memory select signal. All enable bits default
to 1 at reset, except the BMS bit.
See
Figure 10
and
Figure 11
for illustration of the program-
mable flag and composite control register and the system
control register.
Table 10. Wait States
Address Range
Wait State Register
0x000–0x1FF
IOWAIT0 and Wait State Mode
Select Bit
IOWAIT1 and Wait State Mode
Select Bit
IOWAIT2 and Wait State Mode
Select Bit
IOWAIT3 and Wait State Mode
Select Bit
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Figure 9. Wait State Control Register
Figure 10. Programmable Flag and Composite Control
Register
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
RANGING FROM 0 TO 15)
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0X3FFE)
WAIT STATE CONTROL
11 10
9
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15 14
13 12
7
6
5
4
3
2
1
0
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES,
RANGING FROM 0 TO 7)
BMWAIT
CMSSEL
0 = DISABLE
CMS
1 = ENABLE
CMS
DM(0X3FE6)
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2187NBST-320 | RESISTOR, FILM, CHIP (CHIP SIZE: 0805) |
| ADSP-2187NKCA-320 | DSP Microcomputer |
| ADSP-2187NKST-320 | DSP Microcomputer |
| ADSP-2188NKCA-320 | DSP Microcomputer |
| ADSP-2188NKST-320 | DSP Microcomputer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2187NBST-320 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 80MHz 80MIPS 100-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| ADSP-2187NBSTZ-320 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2187NBSTZ-3202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2187NKCA-320 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 80MHz 80MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:32K PM/32K DM RAM,16-BIT,80 MIPS, 1.8V - Bulk |
| ADSP-2187NKST-320 | 制造商:Rochester Electronics LLC 功能描述:32K PM/32K DM RAM,16-BIT, 80 MIPS, 1.8V - Bulk 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
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