參數(shù)資料
型號： ADSP-2186BSTZ-160
廠商： Analog Devices Inc
文件頁數(shù)： 34/36頁
文件大小： 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標準包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機接口，串行端口
時鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 40kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
ADSP-2186
–7–
REV. B
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
A0–A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
CS
DATA
ADDR
DATA
ADDR
2048 LOCATIONS
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
D23–0
A13–0
D23–8
A10–0
D15–8
D23–16
A13–0
14
24
FL0–2
PF3
CLKIN
XTAL
ADDR13–0
DATA23–0
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
ADSP-2186
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
CONTROLLER
16
1
16
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
IDMA PORT
FL0–2
PF3
CLKIN
XTAL
ADDR0
DATA23–8
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ADSP-2186
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
FULL MEMORY MODE
1/2x CLOCK
OR
CRYSTAL
PWDACK
Figure 2. Basic System Configuration
Clock Signals
The ADSP-2186 can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information on this power-down feature,
refer to the ADSP-218x DSP Hardware Reference.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2186 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2186 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used.
A clock output (CLKOUT) signal is generated by the proces-
sor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
CLKIN
CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
Reset
The
RESET signal initiates a master reset of the ADSP-2186.
The
RESET signal must be asserted during the power-up
sequence to assure proper initialization.
RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the
RESET signal should be held low. On
any subsequent resets, the
RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
The
RESET input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET signal, the use of an
external Schmidt trigger is recommended.
相關PDF資料
PDF描述
ADSP-2186MKCA-300 IC DSP CONTROLLER 16BIT 144MBGA
ADSP-2187LBSTZ-210 IC DSP CONTROLLER 16BIT 100-TQFP
ADSP-2188MKSTZ-300 IC DSP CONTROLLER 16BIT 100LQFP
ADSP-2189MKCA-300 IC DSP CONTROLLER 16BIT 144MBGA
ADSP-2189NBCA-320 IC DSP 16BIT 80MHZ 144CSPBGA
相關代理商/技術參數(shù)
參數(shù)描述
adsp-2186kst-1 制造商:Analog Devices 功能描述:
ADSP-2186KST-115 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,33MHZ,16K WORD RAM, 100TQFP - Bulk 制造商:Analog Devices 功能描述:DSP microcomputer 28.8 MHz speed 1 tim
ADSP-2186KST-133 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP FIX PT 16BIT 33.3MHZ 33.3MIPS 100LQFP - Bulk 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT
ADSP-2186KST-160 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:5V 16BIT DSP,40MIPS,8KWORDSPM/DM,100TQFP - Bulk 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT
ADSP-2186KST-1606 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*