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參數(shù)資料
| 型號： | ADSP-2184NKCA-320 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 40 MHz, OTHER DSP, PBGA144 |
| 封裝： | MO-205AC, BGA-144 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | ADSP-2184NKCA-320 |
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ADSP-218xN Series
–16–
REV. 0
Byte Memory Select
The ADSP-218xN’s BMS disable feature combined with
the CMS pin allows use of multiple memories in the byte
memory space. For example, an EPROM could be attached
to the BMS select, and a flash memory could be connected
to CMS. Because at reset BMS is enabled, the EPROM
would be used for booting. After booting, software could
disable BMS and set the CMS signal to respond to BMS,
enabling the flash memory.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data.
Byte memory is accessed using the BDMA feature. The byte
memory space consists of 256 pages, each of which is
16K
8 bits.
The byte memory space on the ADSP-218xN series sup-
ports read and write operations as well as four different data
formats. The byte memory uses data bits 15–8 for data. The
byte memory uses data bits 23–16 and address bits 13–0
to create a 22-bit address. This allows up to a 4 meg
(32 megabit) ROM or RAM to be used without glue logic.
All byte memory accesses are timed by the BMWAIT reg-
ister and the wait state mode bit.
8
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller (
Figure 12
) allows
loading and storing of program instructions and data using
the byte memory space. The BDMA circuit is able to access
the byte memory space while the processor is operating
normally and steals only one DSP cycle per 8-, 16-, or 24-
bit word transferred.
The BDMA circuit supports four different data formats that
are selected by the BTYPE register field. The appropriate
number of 8-bit accesses are done from the byte memory
space to build the word size selected.
Table 11
shows the
data formats supported by the BDMA circuit.
Unused bits in the 8-bit data memory formats are filled with
0s. The BIAD register field is used to specify the starting
address for the on-chip memory involved with the transfer.
The 14-bit BEAD register specifies the starting address for
the external byte memory space. The 8-bit BMPAGE reg-
ister specifies the starting page for the external byte memory
space. The BDIR register field selects the direction of the
transfer. Finally, the 14-bit BWCOUNT register specifies
the number of DSP words to transfer and initiates the
BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequen-
tial addressing. A BDMA interrupt is generated on the com-
pletion of the number of transfers specified by the
BWCOUNT register.
The BWCOUNT register is updated after each transfer so
it can be used to check the status of the transfers. When
it reaches zero, the transfers have finished and a BDMA
interrupt is generated. The BMPAGE and BEAD registers
must not be accessed by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always
be on-chip program or data memory.
When the BWCOUNT register is written with a nonzero
value the BDMA circuit starts executing byte memory
accesses with wait states set by BMWAIT. These accesses
continue until the count reaches zero. When enough access-
es have occurred to create a destination word, it is trans-
ferred to or from on-chip memory. The transfer takes one
Figure 11. System Control Register
RESERVED, ALWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DM(0X3FFF)
SYSTEM CONTROL
9
8
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0
,
IRQ1
, SCLK
1 = SPORT1
DISABLE
BMS
0 = ENABLE
BMS
1 = DISABLE
BMS
PWAIT
PROGRAM MEMORY
WAIT STATES
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14 13 12 11 10
7
6
5
4
3
2
1
0
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS
SHOULD ALWAYS BE WRITTEN WITH ZEROS.
RESERVED
SET TO 0
Figure 12. BDMA Control Register
Table 11. Data Formats
BTYPE
Internal
Memory Space
Word Size
Alignment
00
Program
Memory
Data Memory
Data Memory
Data Memory
24
Full Word
01
10
11
16
8
8
Full Word
MSBs
LSBs
BDMA CONTROL
13 12 11 10
9
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
15 14
8
7
6
5
4
3
2
1
0
DM (0x3FE3)
BDMA
OVERLAY
BITS
(SEE TABLE 12)
相關(guān)PDF資料 |
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|---|---|
| ADSP-2184NBCA-320 | DSP Microcomputer |
| ADSP-2184NBST-320 | DSP Microcomputer |
| ADSP-2187NBCA-320 | DSP Microcomputer |
| ADSP-2187NBST-320 | RESISTOR, FILM, CHIP (CHIP SIZE: 0805) |
| ADSP-2187NKCA-320 | DSP Microcomputer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP2184NKST320 | 制造商:AD 功能描述:New |
| ADSP-2184NKST-320 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 80MHz 80MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:4K/4K RAM, 16-BIT, 80 MIPS, 1.8V - Bulk 制造商:Analog Devices 功能描述:Digital Signal Processor IC Supply Volta |
| ADSP-2184NKSTZ-320 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2184NKSTZ-3202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP2185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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