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Analog Devices, Inc., 1999
ADSP-2184L
DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAM
TIMER
GENERATORS
DAG 2
DAG 1
SERIAL PORTS
SPORT 1
SPORT 0
4K
16
MDATA
3
24
MEMORY
DATA MEMORY DATA
DATA MEMORY ADDRESS
PROGRI/O
FAND
CBYTE DMA
MEMORY
ADSP-2100 BASE
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
POWER-DOWN
CONTROL
PROGRAM
PROGRAM MEMORY ADDRESS
PROGRAM MEMORY DATA
EDATA
BUS
ADDRESS
BUS
INDMA
PORT
EDATA
BUS
OR
FUL MODE
HOST MODE
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
20K Bytes of On-Chip RAM, Configured as
4K Words On-Chip Program Memory RAM and
4K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port Emulator Interface Supports Debugging
in Final Systems
GENERAL DESCRIPTION
The ADSP-2184L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2184L combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2184L integrates 20K bytes of on-chip memory
configured as 4K words (24-bit) of program RAM and 4K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2184L is available in a 100-lead LQFP
package.
In addition, the ADSP-2184L supports instructions that include
bit manipulations—bit set, bit clear, bit toggle, bit test—ALU
constants, multiplication instruction (x squared), biased round-
ing, result free ALU operations, I/O memory transfers and
global interrupt masking for increased flexibility.
ICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.