參數(shù)資料
型號(hào)： ADSP-2183KST-133
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 16.67 MHz, OTHER DSP, PQFP128
封裝： METRIC, PLASTIC, TQFP-128
文件頁(yè)數(shù)： 13/31頁(yè)
文件大?。?/td> 252K
代理商： ADSP-2183KST-133
ADSP-2183
–13–
REV. C
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching Characteristics
specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications
and the corresponding ADSP-2183 timing parameters, for your
convenience.
Memory
Device
Specification
ADSP-2183 Timing
Timing
Parameter
Parameter
Definition
Address Setup to
Write Start
Address Setup to
Write End
Address Hold Time
t
ASW
A0–A13,
xMS
Setup before
WR
Low
A0–A13,
xMS
Setup before
WR
Deasserted
A0–A13,
xMS
Hold after
WR
Deasserted
Data Setup before
WR
High
Data Hold after
WR
High
RD
Low to Data Valid
A0–A13,
xMS
to Data Valid
t
AW
t
WRA
Data Setup Time
t
DW
Data Hold Time
OE
to Data Valid
Address Access Time t
AA
t
DH
t
RDD
xMS
=
PMS
,
DMS
,
BMS
,
CMS
,
IOMS
.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
t
CK
is defined as 0.5t
CKI
. The ADSP-2183 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). t
CK
values within the range of
0.5t
CKI
period should be substituted for all relevant timing pa-
rameters to obtain the specification value.
Example: t
CKH
= 0.5t
CK
– 7 ns = 0.5 (34.7 ns) – 7 ns = 10.35 ns
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Operating Temperature Range (Ambient) . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADSP-2183KSTZ-133 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin LQFP
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