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參數資料
| 型號： | ADSP-2183BST-115 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 14.4 MHz, OTHER DSP, PQFP128 |
| 封裝： | METRIC, PLASTIC, TQFP-128 |
| 文件頁數： | 10/31頁 |
| 文件大?。?/td> | 252K |
| 代理商： | ADSP-2183BST-115 |
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ADSP-2183
–10–
REV. C
If Go Mode is enabled, the ADSP-2183 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2183 is performing an external memory access
when the external device asserts the
BR
signal, then it will not
three-state the memory interfaces or assert the
BG
signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
When the
BR
signal is released, the processor releases the
BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when
RESET
is active.
The
BGH
pin is asserted when the ADSP-2183 is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re-
lease the bus by deasserting bus request. Once the bus is re-
leased, the ADSP-2183 deasserts
BG
and
BGH
and
executes
the external memory access.
Flag I/O Pins
The ADSP-2183 has eight general purpose programmable in-
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2183’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2183 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2.
FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.
INSTRUCTION SET DESCRIPTION
The ADSP-2183 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2183’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2183 has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
The ICE-Port interface consists of the following ADSP-2183 pins:
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
These ADSP-2183 pins must be connected
only
to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2183 and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2183 in the target system. This causes the
processor to use its
ERESET
,
EBR
and
EBG
pins instead of the
RESET
,
BR
and
BG
pins. The
BG
output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2183BST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin LQFP |
| ADSP-2183BST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3.3V16BITDSP,40MIPS16KWORDSPM/DM,128TQFP - Bulk 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| ADSP-2183BST-160X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| ADSP-2183BST-210X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| ADSP-2183BSTZ-160 | 功能描述:IC DSP CONTROLLER 16BIT 128LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:ADSP-21xx 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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