參數(shù)資料
型號(hào)： ADSP-21065LKCAZ264
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 30/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 196-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（15x15）
包裝： 托盤(pán)
REV. C
ADSP-21065L
–36–
OUTPUT DRIVE CURRENT
SOURCE VOLTAGE – V
80
0
3.50
SOURCE
CURRENT
–
mA
0.50
1.00
1.50
2.00
2.50
3.00
60
–40
–100
–120
20
–20
40
0
–80
–60
3.3V, +25 C
3.6V, –40 C
3.1V, +100 C
3.6V, –40 C
VOL
VOH
3.1V, +85 C
3.1V, +100 C
3.1V, +85 C
3.3V, +25 C
Figure 24. Typical Drive Currents
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by
DV is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by
the following equation:
t
CV
I
DECAY
L
=
D
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 26. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays
DV from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with
DV equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
DV
to be the difference between the ADSP-21065L’s output voltage
and the input threshold for the device requiring the hold time. A
typical
DV will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
VOH (MEASURED)
VOL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tENA
tDECAY
OUTPUT
Figure 25. Output Enable
+1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
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