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參數資料
型號: ADSP-21065LKCAZ264
廠商: Analog Devices Inc
文件頁數: 24/44頁
文件大?。?/td> 0K
描述: IC DSP CTLR 32BIT 196CSPBGA
產品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,串行端口
時鐘速率: 60MHz
非易失內存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 196-BGA,CSPBGA
供應商設備封裝: 196-CSPBGA(15x15)
包裝: 托盤
REV. C
ADSP-21065L
–30–
SDRAM Interface—Bus Master
Use these specifications for ADSP-21065L bus master accesses of SDRAM.
Parameter
Min
Max
Unit
Timing Requirements:
tSDSDK
Data Setup Before SDCLK
2.0
ns
tHDSDK
Data Hold After SDCLK
1.25
ns
Switching Characteristics:
tDSDK1
First SDCLK Rise Delay After CLKIN
9.0 + 6 DT
12.75 + 6 DT
ns
tDSDK2
Second SDCLK Rise Delay After CLKIN
25.5 + 22 DT
29.25 + 22 DT
ns
tSDK
SDCLK Period
16.67
tCK/2
ns
tSDKH
SDCLK Width High
7.5 + 8 DT
ns
tSDKL
SDCLK Width Low
6.5 + 8 DT
ns
tDCADSDK
Command, Address, Data, Delay After SDCLK
1
10.0 + 5 DT
ns
tHCADSDK
Command, Address, Data, Hold After SDCLK
1
4.5 + 5 DT
ns
tSDTRSDK
Data Three-State After SDCLK
9.5 + 5 DT
ns
tSDENSDK
Data Enable After SDCLK
2
6.0 + 5 DT
ns
tSDCTR
SDCLK, Command Three-State After CLKIN
1
5.0 + 3 DT
9.75 + 3 DT
ns
tSDCEN
SDCLK, Command Enable After CLKIN
1
5.0 + 2 DT
10.0 + 2 DT
ns
tSDATR
Address Three-State After CLKIN
–1.0 – 4 DT
3.0 – 4 DT
ns
tSDAEN
Address Enable After CLKIN
1.0 – 2 DT
7.0 – 2 DT
ns
NOTES
1Command = SDCKE,
MSx, RAS, CAS, SDWE, DQM, and SDA10.
2SDRAM controller adds one SDRAM CLK three-stated cycle delay (t
CK/2) on a Read followed by a Write.
SDRAM Interface—Bus Slave
These timing requirements allow a bus slave to sample the bus master’s SDRAM command and detect when a refresh occurs.
Parameter
Min
Max
Unit
Timing Requirements:
tSSDKC1
First SDCLK Rise After CLKIN
6.50 + 16 DT
17.5 + 16 DT
ns
tSSDKC2
Second SDCLK Rise After CLKIN
23.25
34.25
ns
tSCSDK
Command Setup Before SDCLK
*
0.0
ns
tHCSDK
Command Hold After SDCLK
*
2.0
ns
NOTE
*Command = SDCKE, RAS, CAS, and SDWE.
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