參數(shù)資料
型號: ADSP-21020BG-100
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 32/40-Bit IEEE Floating-Point DSP Microprocessor
中文描述: 48-BIT, 25 MHz, OTHER DSP, CPGA223
封裝: CERAMIC, PGA-223
文件頁數(shù): 20/32頁
文件大小: 425K
代理商: ADSP-21020BG-100
ADSP-21020
REV. C
–20–
Memory Write
K/B/T Grade
K/B/T Grade
B/T Grade
K Grade
20 MHz
Min
25 MHz
Min
30 MHz
Min Max
33.3 MHz Frequency Dependency*
Min Max Min
Parameter
Max
Max
Max
Unit
Timing Requirement:
t
DAAK
xACK Delay from Address, Select
t
DWAK
xACK Delay from
xWR
Low
t
SAK
xACK Setup before CLKIN High
t
HAK
xACK Hold after CLKIN High
12
6
27
15
18
10
9
5
27 + 7DT/8
15 + DT/2
ns
ns
ns
ns
10
0
14
0
12
0
9
0
14 + DT/4
Switching Characteristic:
t
DAWH
Address, Select to
xWR
Deasserted
t
DAWL
Address, Select to
xWR
Low
t
WW
xWR
Pulse Width
t
DDWH
Data Setup before
xWR
High
t
DWHA
Address, Select Hold after
xWR
Deasserted
t
HDWH
Data Hold after
xWR
Deasserted
1
t
DAP
xPAGE Delay from Address, Select
t
DCKWL
CLKIN High to
xWR
Low
t
WWR
xWR
High to
xWR
or
xRD
Low
t
DDWR
Data Disable before
xWR
or
xRD
Low
t
WDE
xWR
Low to Data Enabled
37
11
26
23
28
7
20
18
21
5
16
14
18
3
15
13
37+ 15DT/16
11 + 3DT/8
26 + 9DT/16
23 + DT/2
ns
ns
ns
ns
1
0
0
–1
0
–1
0
–1
1 + DT/16
DT/16
ns
ns
ns
ns
ns
1
26
1
24
1
22
1
21
16
17
13
13
12
10
11
8
16 + DT/4 26 + DT/4
17 + 7DT/16
13
0
9
–1
7
–1
5
–1
13 + 3DT/8
DT/16
ns
ns
NOTES
*DT = t
C
– 50 ns
See “System Hold Time Calculation” in “Test Conditions” section for calculating hold times given capacitive and DC loads.
x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select =
PMS1-0
,
DMS3-0
.
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