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參數(shù)資料
| 型號： | ADS7852Y |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-CDIP -55 to 125 |
| 中文描述： | 12位，8通道，并行輸出的模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 148K |
| 代理商： | ADS7852Y |
12
ADS7852
FIGURE 3. Entering Nap Using RD and A0.
FIGURE 4. Initiating Wake-Up Using RD and A0.
POWER-DOWN MODE
The ADS7852 has two different power-down modes: the
Nap mode and the Sleep mode. In the Nap mode, all analog
and digital circuitry, with the exception of the voltage
reference, is powered off. In the Sleep mode, everything is
powered off.
While the Sleep mode affords the lowest power consump-
tion, the time to come out of Sleep mode can be considerable
since it takes the internal reference voltage a finite amount of
time to power up and reach a stable value. This latency can
result in spurious output data for a minimum of ten conver-
sion cycles at a 500kHz sampling rate. It should also be
noted that any external load connected to the V
REF
pin will
exacerbate this effect since a discharge path for the V
REF
bypass capacitor is provided during the Sleep cycle. Even the
parasitic leakage of the bypass capacitor itself should be
considered if the unit is left in the Sleep mode for an
extended period. After power-up, this capacitor must be
recharged by the internal reference voltage and the on-chip
10k
series resistor. Under worst-case conditions (e.g., the
bypass capacitor is completely discharged), the output data
can be invalid for several hundred milliseconds.
Since the Nap mode maintains the voltage on the V
REF
pin by
keeping the internal reference powered-up, valid conversions
are available immediately after the Nap mode is terminated.
The simplest way to use the power-down mode is following
a conversion. After a conversion has finished and BUSY has
returned HIGH, CS and RD must be brought LOW for a
minimum of 25ns. When RD and CS are returned HIGH, the
ADS7852 will enter the power-down mode on the rising
edge of RD. If CS is always kept LOW, the power-down
mode will be controlled exclusively by RD. Depending on
the status of the A0 and A1 address pins, the ADS7852 will
either enter the Nap mode, the Sleep mode, or be returned
to normal operation in the sampling mode. See Table II and
Figures 3 and 4 for further details.
RD
A2
A1
A0
POWER-DOWN MODE
X
0
0
None
X
1
0
Sleep
X
0
1
Nap
X
1
1
Sleep
= Signifies rising edge of RD pin. X = Don't care
TABLE II. ADS7852 Power-Down Mode.
CS
RD
CLK
BUSY
A0
A1
t
11
t
12
t
7
t
8
t
6
NOTE: Rising edge of 1
st
RD while A0 = 1 initiates power-down immediately. A1 must be LOW to enter Nap mode.
t
13
t
14
CS
RD
CLK
A1
A0
t
11
t
12
t
7
t
8
t
6
t
15
NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7852 in sample mode. A1 must be LOW to initiate wake-up.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7852Y/250 | 功能描述:模數(shù)轉換器 - ADC 12-Bit 8-Channel Parallel Output RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7852Y/250G4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit 8-Channel Parallel Output RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7852Y/2K | 功能描述:模數(shù)轉換器 - ADC 12-Bit 8-Channel Parallel Output RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7852Y/2KG4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit 8-Channel Parallel Output RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7852YB | 制造商:Texas Instruments 功能描述:12BIT ADC PARALLEL O/P SMD 7852 |
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