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參數(shù)資料
| 型號： | ADS7841PB |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-SO -55 to 125 |
| 中文描述： | 12位，4通道串行輸出采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 277K |
| 代理商： | ADS7841PB |
12
ADS7841
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW,
the device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
16-Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7841 is fully powered while other serial communica-
tions are taking place.
Digital Timing
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
PD1
0
PD0
0
Description
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
0
1
Reserved for future use.
1
0
Reserved for future use.
1
1
No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
BD
t
BDV
t
BTR
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
DCLK LOW
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
1.5
100
10
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
200
200
100
0
200
200
200
200
200
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= –40
°
C to +85
°
C, C
LOAD
= 50pF).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
BD
t
BDV
t
BTR
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
DCLK LOW
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
900
50
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
70
70
50
0
150
150
100
70
70
TABLE VII. Timing Specifications (+V
CC
= +4.75V to
+5.25V, T
A
= –40
°
C to +85
°
C, C
LOAD
= 50pF).
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
1
DCLK
CS
11
DOUT
BUSY
A2
S
DIN
A1 A0
MODEDIF
PD1 PD0
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
6
5
4
3
2
A1 A0
15
1
15
1
A2
S
A1 A0
MODEDIF
PD1 PD0
A2
S
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| ADS7842EB | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-TSSOP -55 to 125 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7841PB | 制造商:Texas Instruments 功能描述:IC 12BIT ADC 7841 PDIP16 |
| ADS7841PBG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 4-Ch Serial Output Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7841PG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 4-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7841-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT 4-CHANNEL SERIAL-OUTPUT SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| ads7841qdbqrrb | 制造商:Texas Instruments 功能描述:A/D CONV 12-BIT 4-CHANNEL 16LD |
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