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參數(shù)資料
| 型號： | ADS7841PB |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-SO -55 to 125 |
| 中文描述： | 12位，4通道串行輸出采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 277K |
| 代理商： | ADS7841PB |
10
ADS7841
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7841 will operate with a reference in the range of
100mV to +V
CC
. Keep in mind that the analog input is the
difference between the +IN input and the –IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH3) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is re-
duced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the A/D
converter will appear to increase, in terms of LSB size, as the
reference voltage is reduced. For example, if the offset of a
given converter is 2 LSBs with a 2.5V reference, then it will
typically be 10 LSBs with a 0.5V reference. In each case, the
actual offset of the device is the same, 1.22mV.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24
μ
V. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS7841. Typically, the input current is
13
μ
A with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
Figure 3 shows the typical operation of the ADS7841’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +V
CC
). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next twelve clock cycles accomplish the actual analog-
to-digital conversion. A thirteenth clock cycle is needed for
the last bit of the conversion result. Three more clock cycles
are needed to complete the last byte (DOUT will be LOW).
These will be ignored by the converter.
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7841 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
The MODE bit and the MODE pin work together to deter-
mine the number of bits for a given conversion. If the
MODE pin is LOW, the converter always performs a 12-bit
conversion regardless of the state of the MODE bit. If the
MODE pin is HIGH, then the MODE bit determines the
number of bits for each conversion, either 12 bits (LOW) or
8 bits (HIGH).
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
S
A2
A1
A0
MODE
SGL/DIF
PD1
PD0
TABLE III.Order of the Control Bits in the Control Byte.
TABLE IV.Descriptions of the Control Bits within the
Control Byte.
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
6 - 4
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
3
MODE
12-Bit/8-Bit Conversion Select Bit. If the MODE pin
is HIGH, this bit controls the number of bits for the
next conversion: 12-bits (LOW) or 8-bits (HIGH). If
the MODE pin is LOW, this bit has no function and
the conversion is always 12 bits.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
1 - 0
PD1 - PD0
Power-Down Mode Select Bits. See Table V for
details.
相關(guān)PDF資料 |
PDF描述 |
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| ADS7842 | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-SO -55 to 125 |
| ADS7842E | 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7842EB | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-TSSOP -55 to 125 |
| ADS7843 | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-TSSOP -55 to 125 |
| ADS7843E | CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-PDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7841PB | 制造商:Texas Instruments 功能描述:IC 12BIT ADC 7841 PDIP16 |
| ADS7841PBG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 4-Ch Serial Output Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7841PG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 4-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7841-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT 4-CHANNEL SERIAL-OUTPUT SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| ads7841qdbqrrb | 制造商:Texas Instruments 功能描述:A/D CONV 12-BIT 4-CHANNEL 16LD |
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