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參數(shù)資料
| 型號(hào)： | ADS7833N |
| 英文描述： | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| 中文描述： | 10通道，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 150K |
| 代理商： | ADS7833N |
ADS7833
9
PGA GAIN
The PGA gain is determined by the Gain Select portion (bits
8 and 9) in the SER
IN
word (see Figure 2). There is one gain
input that sets the same gain for all three PGAs. The gain
values and allowable full scale inputs are shown in Table II.
For channels one and two the PGAs set the gain for all three
analog inputs. For the third channel, only the V
3-1
input is
gain changed by the PGA. Inputs V
3-2
, V
3-3
and V
3-4
are
connected to ADC
3
at a fixed gain of 1V/V regardless of the
Gain Select value.
Input Select = 3
H
—Convert V
1-3
via SH
2
, V
2-3
via SH
4
,
and V
3-3
(V
1-3
and V
2-3
are from the value sampled in a
preceding conversion cycle with Input Select = 4
H
, 5
H
or
6
H
).
Input Select = 2
H
—Convert V
1-3
via SH
1
, V
2-3
via SH
3
,
and V
3-3
(V
1-3
is sampled on SH
2
in this conversion cycle).
Input Select = 1
H
—Input V
3-4
is converted by PGA
3
/
ADC
3
. The output of the asynchronous sample holds, SH
6
and SH
7
, are converted by PGA
1
/ADC
1
and PGA
2
/ADC
2
,
respectively. Note that the inputs to SH
6
and SH
7
are
determined by previous Input Select values (see Table IV).
Thus, to properly convert the output of one of the asynchro-
nous sample holds it is first necessary to choose its input
with a previous conversion cycle. Also, the output of SH
6
or
SH
7
will only be converted if ASH goes low before the
CONV command is received.
Input Select = 0
H
—V
3-4
is converted by PGA
3
/ADC
3
. The
inputs to PGA
1
/ADC
1
and PGA
2
/ADC
2
are undefined.
CONVERSIONS FROM THE
ASYNCHRONOUS SAMPLE HOLDS
Decoding the Input Select value also determines which
inputs are applied to the two asynchronously controlled
sample holds SH
6
and SH
7
. (See Table IV.) One of the three
possible inputs is selected by the Input Select value being 4,
5, or 6.
The “No Effect” states indicate that these values of Input
Select have no effect on the multiplexers at the input of SH
6
and SH
7
. When one of the “No Effect” values of Input Select
is presented, the multiplexers will not be changed (i.e., their
condition is determined by the last 4, 5, or 6 value of Input
Select that existed prior to the “No Effect” state).
Note that Input Select = 1
H
presents the output of SH
6
and
SH
7
(1ASH
X
and 2ASH
X
) to PGA
1
/ADC
l
and PGA
2
/ADC
2
,
respectively (see Table III). Therefore, in order to properly
convert the asynchronous sampled signals, it is first neces-
sary to choose an input signal (Input Select equal 5 or 6 in
Table IV) with one load/convert cycle and then convert the
sample hold output (Input Select = 4 in Table III) in a
following conversion cycle.
GAIN
SELECT
0-1
GAIN
SETTING
FULL SCALE
INPUT
0
H
1
H
2
H
3
H
5.0V/V
2.5V/V
1.25V/V
1.0V/V
±
0.5V
±
1.0V
±
2.0V
±
2.5V
TABLE II. Gain Select Information.
INPUT MULTIPLEXER AND
SAMPLE HOLD SELECTION
The Input Select portion of the SER
IN
word (bits 10, 11 and
12) (see Figure 2) are decoded and determine the
open/closed condition of the multiplexer switches. This in
turn determines which input signals are connected to the
sample holds and which sample holds are connected to the
PGAs/ADCs.
INPUT SIGNALS FOR PGAs/ADCs
Table III shows the relationships between the value of Input
Select
0-2
and the signals that are converted.
INPUT SELECT
0-2
HEX
CODE
ANALOG SIGNAL CONNECTED TO
PGA
X
/ADC
X
PGA
1
/ADC
1
PGA
2
/ADC
2
Undefined
Undefined
V
1-X
via SH
6(1)
V
2-X
via SH
7(1)
V
1-3
via SH
1
V
2-3
via SH
3
V
1-3
via SH
2
V
2-3
via SH
4
V
1-2
V
1-2
V
1-2
V
1-1
PGA
3
/ADC
2
V
3-4
V
3-4
V
3-3
V
3-3
V
3-2
V
3-2
V
3-2
V
3-1
0
H
1
H
2
H
3
H
4
H
5
H
6
H
7
H
000
001
010
011
100
101
110
111
V
2-2
V
2-2
V
2-2
V
2-1
NOTE: (1) See Table IV for Operation.
BINARY
CODE
TABLE III. Input Controls for Synchronous Sample Holds.
Input Select = 7
H
—Synchronously sample and convert
input signals V
1-1
, V
2-1
, and V
3-1
.
Input Select = 4
H
, 5
H
, 6
H
—Synchronously sample and
convert input signals V
1-2
, V
2-2
, and V
3-2
. These codes also
cause SH
2
and SH
4
to sample their inputs. Values 4
H
, 5
H
, 6
H
have different effects on the inputs to SH
6
and SH
7
(see
Table IV).
INPUT SELECT
0-2
HEX
CODE
ANALOG SIGNAL CONNECTED TO
SH
6
SH
7
0
H
1
H
2
H
3
H
4
H
5
H
6
H
7
H
000
001
010
011
100
101
110
111
No Effect
No Effect
No Effect
No Effect
Open
V
1-3
V
1-2
No Effect
No Effect
No Effect
No Effect
No Effect
Open
V
2-3
V
1-2
No Effect
BINARY
CODE
TABLE IV. Input Controls for Asynchronous Sample Holds.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7834 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
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| ADS7834E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADS7834E/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7834E/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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