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參數(shù)資料
| 型號： | ADS7832BP |
| 英文描述： | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | Autocalibrating，4通道，12位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 299K |
| 代理商： | ADS7832BP |
ADS7832
10
PIN
FUNCTION
DESCRIPTION
D0
Mode Status
If LOW, Transparent Mode enabled for
data latches. If HIGH, latched Output
Mode enabled.
If HIGH, calibration cycle in progress.
If LOW, pin 26 used as input to initiate
calibration cycle. If HIGH, pin 26 used
as input to control sample-to-hold timing.
If HIGH, in Power Down Mode (Power
Down Mode is the default condition).
Reserved for factory use.
If HIGH, a power supply failure has
occurred (supply fell below 2.7V).
Always write as LOW.
If HIGH, an overflow occurred during
calibration.
If HIGH, conversion or calibration in
progress.
D1
D2
CAL Flag
Pin 26 Status
D3
Power Down Status
D4
D5
POWER FAIL Flag
D6
CAL ERROR Flag
D7
BUSY Flag
NOTE: These data are transferred to the bus when a read cycle is initiated
with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW
is reserved for factory use at this time, and will yield unpredictable data.
critical parameters are guaranteed over the full –40
°
C to
+85
°
C operating range for ease of system design.
SPECIAL FUNCTION REGISTER (SFR)
An internal register is available, either to determine addi-
tional data concerning the ADS7832, or to write additional
instructions to the converter.
Table II shows the data in the Special Function Register that
will be transferred to the output bus by driving HBE HIGH
(with SFR HIGH) and initiating a read cycle (driving RD
and CS LOW with WR HIGH.) The Power Fail flag in the
SFR is set when the power supply falls below about 2.7V.
The flag also means that a new calibration has been started,
ADS7832 provides two modes for reading the conversion
results. At power-up, the converter is set in the Transparent
Mode.
TRANSPARENT MODE
This is the default mode for ADS7832. In this mode, the
conversion decisions from the successive approximation
register are latched into the output register as they are made.
Thus, the High byte (the 4 MSBs) can be read after the end
of the ninth clock cycle (five clock cycles for the mux
settling, sample acquisition and auto-zeroing of the com-
parator, followed by the four clock cycles for the 4MSB
decisions.) The complete 12-bit data is available after BUSY
has gone HIGH, or the internal status flag goes LOW (D7
when HBE is HIGH).
LATCHED OUTPUT MODE
This mode is activated by writing a HIGH to D0 in the
Special Function Register with CS and WR LOW and SFR
and HBE HIGH. (See the discussion of the Special Function
Register below.)
In this mode, the data from a conversion is latched into the
output buffers only after a conversion is complete, and
remains there until the next conversion is completed. The
conversion result is valid during the next conversion. This
allows the data to be read even after a new conversion is
started, for faster system throughput.
TIMING CONSIDERATIONS
Table I and Figures 3 through 9 show the digital timing of
ADS7832 under the various operating modes. All of the
TABLE II. Reading the Special Function Register.
SYMBOL
PARAMETER
(1)
MIN
TYP
MAX
UNITS
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
CS to WR Setup Time
(2)
WR or CAL Pulse Width
CS to WR Hold Time
(2)
WR to BUSY Propagation Delay
A0, A1, HBE, SFR Valid to WR Setup Time
A0, A1, HBE, SFR Valid to WR Hold Time
BUSY to CS Setup Time
CS to RD Setup Time
(2)
RD Pulse Width
CS to RD Hold Time
(2)
HBE, SFR to RD Setup Time
HBE, SFR to RD Hold Time
RD to Valid Data (Bus Access Time)
(3)
RD to Hi-Z Delay (Bus Release Time)
(3)
RD to Hi-Z Delay For SFR
(3)
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Acquisition Time. Pin 26 LOW with D2 in SFR HIGH
Sample-to-Hold Aperture Delay. (D2 in SFR HIGH)
Delay from rising edge on pin 26 to start of conversion.
(D2 in SFR HIGH)
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
100
0
20
0
20
0
0
100
0
50
0
0
50
0
150
0
0
0
0
80
90
150
180
60
20
100
20
2.5
5
1.5
CLK cycles
NOTES: (1) All input control signals are specified with t
RISE
= t
FALL
= 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from V
IH
,
V
IL
, V
OH
or V
OL
. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR.
(3) Figures 8 and 9 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states.
TABLE I. Timing Specifications (CLK = 2MHz external, T
A
= –40
°
C to +85
°
C).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7833 | 制造商:BB 制造商全稱:BB 功能描述:10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| ADS7833N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADS7834 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7834_13 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit High-Speed, Low-Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7834E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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