參數(shù)資料
型號: ADS7831P
英文描述: 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER
中文描述: 12位600kHz的采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 9/10頁
文件大?。?/td> 313K
代理商: ADS7831P
9
ADS7831
FIGURE 4a. Circuit Diagram With External Hardware Trim.
FIGURE 4b. Circuit Diagram Without External Hardware Trim.
CALIBRATION
The ADS7831 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain.
Hardware Calibration
To calibrate the offset and gain of the ADS7831, install the
proper resistors and potentiometers as shown in Figure 4a.
The calibration range is
±
12mV for the offset and
±
30mV
for full scale.
Potentiometer P
and resistor R
form the offset adjust
circuit and P
and R
the gain adjust circuit. The exact values
are not critical. R
and R
should not be made any larger than
the value shown. They can easily be made smaller to
provide increased adjustment range. Reducing these below
15% of the indicated values could begin to adversely affect
the operation of the converter.
P
and P
can also be made larger to reduce power dissipa-
tion. However, larger resistances will push the useful adjust-
ment range to the edges of the potentiometer. P
should
probably not exceed 20k
and P2 100k
in order to main-
tain reasonable sensitivity.
Software Calibration or No Calibration
The ADS7831 does not require external resistors for its
basic operation. However, the component is designed to be
used with an external 50
resistor on the input, and the
specifications apply to this condition. If this resistor is not
used, the only specification that will be affected is total
unadjusted error.
With the 50
resistor, the nominal input voltage range is
±
2.5V and the total unadjusted error is
±
10LSBs guaran-
teed. Without the 50
resistor, the nominal input voltage
range will be
±
2.46V and the total unadjusted error is not
guaranteed. While it will typically be much less, the total
unadjusted error could be as high as
±
20LSBs.
50
AGND2
CAP
REF
AGND1
V
IN
+
0.1μF
10μF
V
IN
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 2.5V.
FIGURE 3. Using CS to Control Conversion and Read Timing.
t
9
Hi-Z State
BUSY
CS
R/C
DATA
BUS
MODE
Acquire
Data Valid
HI Z State
Convert
t
7
t
2
t
6
t
3
t
4
t
11
t
5
Acquire
t
13
t
11
t
1
t
11
t
11
50
AGND2
CAP
REF
AGND1
V
IN
+
0.1μF
10μF
V
IN
+5V
R
1
20k
R
2
604k
–5V
P
1
5k
P
2
5k
+5V
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