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參數(shù)資料
| 型號(hào)： | ADS7831P |
| 英文描述： | 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位600kHz的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 313K |
| 代理商： | ADS7831P |
8
ADS7831
t
9
Hi-Z State
t
8
BUSY
R/C
DATA BUS
MODE
Acquire
Data Valid
t
10
Data Valid
HI Z State
Convert
Convert
t
7
t
6
t
3
t
4
t
1
t
2
t
5
Acquire
t
12
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
The nominal input impedance of 3.125k
results from the
combination of the internal resistor network shown on page 3
of this data sheet and the external 50
resistor. The input
resistor divider network provides inherent over-voltage pro-
tection guaranteed to at least
±
25V. The 50
, 1% resistor
does not compromise the accuracy or drift of the converter. It
has little influence relative to the internal resistors, and tighter
tolerances are not required.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by
±
30%. This is
true of all resistors internal to the ADS7831. Each resistive
divider is trimmed so that the proper division is achieved.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
READING DATA
The ADS7831 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when R/C (pin 23) is HIGH, CS (pin 24)
is LOW, and
no conversion is in progress. Any other combination will tri-
state the parallel output. Valid conversion data can be read in
a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-18).
Refer to Table II for ideal output codes.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2 and 3.
Note: For best performance, the external data bus connected
to D11-D0 should not be active during a conversion. The
switching noise of the external asynchronous data signals
can cause digital feed through degrading the converter’s
performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
ANALOG INPUT
The ADS7831 has a
±
2.5V input range. Figures 4a and 4b
show the necessary circuit connections for the ADS7831
with and without external trim. Offset and full scale error
(1)
specifications are tested and guaranteed with the 50
resis-
tor shown in Figure 4b. This external resistor makes it
possible to trim the offset
±
12mV using R
and P
as shown
in Figure 4a. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration
section of the data sheet for details.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
Convert Pulse Width
40
ns
t
2
Data Valid Delay
After Start of Conversion
1310
1460
ns
t
3
BUSY Delay
From Start of Conversion
75
125
ns
t
4
BUSY LOW
1300
1440
ns
t
5
BUSY Delay After
End of Conversion
90
ns
t
6
Aperture Delay
20
ns
t
7
Conversion Time
1285
1400
ns
t
8
Acquisition Time
200
250
ns
t
7
& t
8
Throughput Time
1485
1650
ns
t
9
Bus Relinquish Time
10
55
83
ns
t
10
BUSY Delay
After Data Valid
20
65
100
ns
t
11
R/C to CS
Setup Time
10
ns
t
12
Time Between
Conversions
1660
ns
t
13
Bus Access Time
10
30
62
ns
TABLE III. Timing Specifications (T
MIN
to T
MAX
).
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADS7831U | 制造商:BB 制造商全稱:BB 功能描述:12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7832 | 制造商:BB 制造商全稱:BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7832BN | 制造商:Rochester Electronics LLC 功能描述: |
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| ADS7833 | 制造商:BB 制造商全稱:BB 功能描述:10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
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