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參數(shù)資料
| 型號： | ADS7820PB |
| 英文描述： | 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位10ms的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 280K |
| 代理商： | ADS7820PB |
ADS7820
7
READING DATA
The ADS7820 outputs full or byte-reading parallel data in
Straight Binary data output format. The parallel output will
be active when R/C (pin 24) is HIGH and CS (pin 25) is
LOW. Any other combination of CS and R/C will tri-state
the parallel output. Valid conversion data can be read in a
full parallel, 12-bit word or two 8-bit bytes on pins 6-13 and
pins 15-22. BYTE (pin 23) can be toggled to read both bytes
within one conversion cycle. Refer to Table II for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 16
μ
s
after the start of conversion ‘n’. Do not attempt to read data
from 16
μ
s after the start of conversion ‘n’ until BUSY (pin
26) goes HIGH; this may result in reading invalid data.
Refer to Table III and Figures 3 and 5 for timing specifica-
tions.
Note!
For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough degrad-
ing the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D11-D0 (pin 6-13
and 15-18 when BYTE is LOW). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 3 and
5 for timing specifications.
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full Scale Range
0 to +5V
Least Significant
Bit (LSB)
1.22mV
Full Scale
4.99878V
1111 1111 1111
FFF
Midscale
2.5V
1000 0000 0000
800
One LSB below
Midscale
2.49878V
0111 1111 1111
7FF
Zero Scale
0V
0000 0000 0000
0
Table II. Ideal Input Voltages and Output Codes.
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
1
Convert Pulse Width
40
5400
ns
t
2
Data Valid Delay after R/C LOW
8
μ
s
t
3
t
4
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
μ
s
t
5
BUSY Delay after
End of Conversion
220
ns
t
6
Aperture Delay
40
ns
t
7
Conversion Time
7.6
8
μ
s
t
8
Acquisition Time
2
μ
s
t
9
Bus Relinquish Time
10
35
83
ns
t
10
BUSY Delay after Data Valid
50
200
ns
t
11
Previous Data Valid
after R/C LOW
7.4
μ
s
t
7
+ t
6
Throughput Time
9
10
μ
s
t
12
R/C to CS Setup Time
10
ns
t
13
Time Between Conversions
10
μ
s
t
14
Bus Access Time
and BYTE Delay
10
83
ns
TABLE III. Conversion Timing.
LOW
LOW
LOW
LOW
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 11 (MSB)
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7820
BYTE LOW
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
LOW
LOW
LOW
LOW
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7820
BYTE HIGH
+5V
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADS7820U | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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