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4
ADS7820
1
2
3
V
IN
Analog Input. Full-scale input range is 0 to +5V.
Analog Ground. Used internally as ground reference point.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both
cases, connect to ground with a 2.2
μ
F Tantalum capacitor.
Reference Buffer Capacitor. 2.2
μ
F Tantalum to ground.
Analog Ground.
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Byte Select. With BYTE LOW, data will be output as indicated above, causing pin 6 (D11) to output the MSB, and pin 18 (D0) to
output the LSB. Pins 19 to 22 will output LOWs. With BYTE HIGH, the top and bottom 8 bits of data will be switched, so that pin 6
outputs data bit 3, pin 9 outputs data bit 0 (LSB), pin 10 to 13 output LOWs, pin 15 outputs data bit 11 (MSB) and pin 22 outputs
data bit 4.
Read/Convert input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
With CS LOW, a rising edge on R/C enables the output data bits.
Chip Select. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge
on CS will enable the output data bits.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to
latch the data. CS or R/C must be high when BUSY rises, or another conversion will start, without time for signal acquisition.
Analog Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1
μ
F ceramic and 10
μ
F Tantalum
capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be
≤
V
ANA
.
AGND1
REF
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
D3
D2
D1
D0 (LSB)
DZ
DZ
DZ
DZ
BYTE
24
R/C
25
CS
26
BUSY
27
V
ANA
28
V
DIG
PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
DZ
DZ
DZ
DZ
D0 (LSB)
D1
D2
D3
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7820
PIN #
NAME
DESCRIPTION
PIN ASSIGNMENTS