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參數(shù)資料
| 型號： | ADS7819U |
| 英文描述： | 12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位800kHz采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 317K |
| 代理商： | ADS7819U |
8
ADS7819
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the
Reading Data
section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
READING DATA
The ADS7819 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tri-state
the parallel output. Valid conversion data can be read in a full
parallel, 12-bit word on D11-D0 (pins 6-13 and 15-18). Refer
to Table II for ideal output codes.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2 and 3.
Note: For best performance, the external data bus connected
to D11-D0 should not be active during a conversion. The
switching noise of the external asynchronous data signals
can cause digital feed through degrading the converter’s
performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
INPUT RANGES
The ADS7819 has a
±
2.5V input range. Figures 4a and 4b
show the necessary circuit connections for the ADS7819
with and without external hardware trim. Offset and full
scale error
(1)
specifications are tested and guaranteed with
the 50
resistor shown in Figure 4b. This external resistor
makes it possible to trim the offset
±
12mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration
section of the data sheet for details.
The nominal input impedance of 3.125k
results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external 50
resistor. The input resistor divider network provides inherent
over-voltage protection guaranteed to at least
±
25V. The
50
, 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by
±
30%. This is
true of all resistors internal to the ADS7819. Each resistive
divider is trimmed so that the proper division is achieved.
NOTE: (1) Full scale error includes offset and gain errors and is measured at
both +FS and –FS.
TABLE III. Timing Specifications (T
MIN
to T
MAX
).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
Convert Pulse Width
40
ns
t
2
Data Valid Delay
After Start of Conversion
965
1100
ns
t
3
BUSY Delay
70
125
ns
From Start of Conversion
t
4
BUSY LOW
960
1085
ns
t
5
BUSY Delay After
End of Conversion
90
ns
t
6
Aperture Delay
20
ns
t
7
Conversion Time
940
1030
ns
t
8
Acquisition Time
180
220
ns
t
7
& t
8
Throughput Time
1120
1250
ns
t
9
Bus Relinquish Time
10
50
83
ns
t
10
BUSY Delay
After Data Valid
20
65
100
ns
t
11
R/C to CS
Setup Time
10
ns
t
12
Time Between
Conversions
1250
ns
t
13
Bus Access Time
10
30
62
ns
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