參數(shù)資料
型號(hào)： ADS7806U
英文描述： Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
中文描述： 低功耗12位采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/18頁(yè)
文件大?。?/td> 209K
代理商： ADS7806U
9
ADS7806
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going high can be used to latch the data.
Refer to Table VI and Figures 2 and 3 for timing constraints.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12
μ
s
after the start of conversion ‘n’. Do not attempt to read data
beyond 12
μ
s after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table VI and Figures 2 and 3 for timing constraints.
port will shift the internal output registers one bit per data
clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.
PARALLEL OUTPUT
To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when R/C
(pin 22) is HIGH and CS (pin 23) is LOW. Any other
combination of CS and R/C will tri-state the parallel output.
Valid conversion data can be read in two 8-bit bytes on D7-
D0 (pins 9-13 and 15-17) . When BYTE (pin 21) is LOW,
the 8 most significant bits will be valid with the MSB on D7.
When BYTE is HIGH, the 4 least significant bits will be
valid with the LSB on D4. BYTE can be toggled to read both
bytes within one conversion cycle.
Upon initial power up, the parallel output will contain
indeterminate data.
t
10
BUSY
R/C
MODE
Acquire
Convert
t
11
t
7
t
6
t
3
t
4
t
1
Acquire
Convert
t
8
t
6
t
3
Parallel
Data Bus
Previous
High Byte Valid
t
12
Hi-Z
Not Valid
t
2
t
9
High Byte
Valid
t
12
t
9
t
12
BYTE
t
1
Previous Low
Byte Valid
Previous High
Byte Valid
Low Byte
Valid
High Byte
Valid
t
12
Hi-Z
t
12
t
12
t
5
Hi-Z State
BUSY
R/C
DATA
BUS
High Byte
t
3
t
4
t
21
t
21
t
1
t
21
t
21
BYTE
t
21
t
21
t
21
t
21
t
21
t
21
Hi-Z State
Low Byte
Hi-Z State
t
9
t
12
t
9
t
12
CS
FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS7806U 制造商:Texas Instruments 功能描述:12BIT ADC LOW POWER SERIAL 7806
ADS7806U/1K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7806U/1KE4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7806U/1KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7806UB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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