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參數(shù)資料
| 型號(hào)： | ADS7806 |
| 英文描述： | CMOS Quad 2-Input NOR Gate 14-SOIC -55 to 125 |
| 中文描述： | 低功耗12位采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大小： | 209K |
| 代理商： | ADS7806 |
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10
ADS7806
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
TABLE VI. Conversion and Data Timing. T
A
= –40
°
C to
+85
°
C.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7806 will output 12
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 12 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what-
ever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7806, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions. While this is
perfectly acceptable, there is a possible problem when using
an external data clock. At an indeterminate point from 12
μ
s
after the start of conversion 'n' until BUSY rises, the internal
logic will shift the results of conversion 'n' into the output
register. If CS is LOW, R/C is HIGH, and the external clock
is HIGH at this point, data will be lost. So, with CS LOW,
either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
t
1
Convert Pulse Width
0.04
12
μ
s
t
2
Data Valid Delay after R/C LOW
14.7
20
μ
s
t
3
BUSY Delay from
Start of Conversion
85
ns
t
4
BUSY LOW
14.7
20
μ
s
t
5
BUSY Delay after
End of Conversion
90
ns
t
6
Aperture Delay
40
ns
t
7
Conversion Time
14.7
20
μ
s
t
8
Acquisition Time
5
μ
s
t
9
Bus Relinquish Time
10
83
ns
t
10
BUSY Delay after Data Valid
20
60
ns
t
11
Previous Data Valid
after Start of Conversion
12
14.7
μ
s
t
12
Bus Access Time and BYTE Delay
83
ns
t
13
Start of Conversion
to DATACLK Delay
1.4
μ
s
t
14
DATACLK Period
1.1
μ
s
t
15
Data Valid to DATACLK
HIGH Delay
20
75
ns
t
16
Data Valid after DATACLK
LOW Delay
400
600
ns
t
17
External DATACLK Period
100
ns
t
18
External DATACLK LOW
40
ns
t
19
External DATACLK HIGH
50
ns
t
20
CS and R/C to External
DATACLK Setup Time
25
ns
t
21
R/C to CS Setup Time
10
ns
t
22
Valid Data after DATACLK HIGH
25
ns
t
7
+ t
8
Throughput Time
25
μ
s
1
MSB Valid
CS or R/C
(1)
DATACLK
SDATA
BUSY
t
7
+ t
8
t
16
t
15
t
14
t
13
2
3
11
12
Bit 10 Valid
Bit 1 Valid
Bit 9 Valid
LSB Valid
NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.
1
MSB Valid
2
Bit 10 Valid
(Results from previous conversion.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7806P | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7806P | 制造商:BURR-BROWN 功能描述:12BIT ADC SAMPLING 7806 DIP28 |
| ADS7806PB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7806PBG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7806PG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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