參數(shù)資料
型號(hào): ADS5240IPAP
元件分類: ADC
英文描述: 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述: 4通道,12位,40MSPS的ADC的串行LVDS接口
文件頁(yè)數(shù): 9/24頁(yè)
文件大小: 418K
代理商: ADS5240IPAP
www.ti.com
TEST PATTERNS
(1)
ADS5240
SBAS326C–JUNE 2004–REVISED DECEMBER 2004
SERIAL INTERFACE REGISTERS
ADDRESS
D6
0
DATA
D2
DESCRIPTION
REMARKS
D7
0
D5
0
D4
0
D3
D1
D0
LVDS BUFFERS (register 0)
Normal ADC Output
Deskew Pattern
Sync Pattern
Custom Pattern
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
LSB/MSB MODE (register 1)
Default LVDS Clock Output Current
2X LVDS Clock Output Current
LSB First Mode
MSB First Mode
POWER-DOWN ADC CHANNELS
(register 2)
D2: Power-Down for Channel 2
D0: Power-Down for Channel 1
POWER-DOWN ADC CHANNELS
(register 3)
D3: Power-Down for Channel 4
D1: Power-Down for Channel 3
CUSTOM PATTERN (registers 4-6)
Bits for Custom Pattern
0
0
1
1
0
1
0
1
(default after reset)
Patterns Get Reversed in MSB
First Mode of LVDS
0
0
1
1
0
1
0
1
(default after reset)
0
0
0
1
0
0
0
0
X
X
0
1
X
X
X
X
0
1
X
X
I
OUT
= 3.5mA
I
OUT
= 7.0mA
(default after reset)
0
0
1
0
0
0
1
X
0
0
X
1
Logic 1 = Channel Powered
Down
0
0
1
1
1
X
0
0
X
1
0
0
Logic 1 = Channel Powered
Down
D3
X
X
X
D2
X
X
X
D1
X
X
X
D0
X
X
X
See
Test Patterns
0
0
0
1
1
1
0
0
1
0
1
0
Deskew
Sync
Custom
101010101010
000000111111
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following
order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1)
Default is LSB first. If MSB first is selected, the above patterns will be reversed.
9
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