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參數(shù)資料
| 型號： | ADS1256 |
| 英文描述： | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| 中文描述： | 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 427K |
| 代理商： | ADS1256 |
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SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
22
Settling Time Using One-Shot Mode
A dramatic reduction in power consumption can be achieved
in the ADS1255/6 by performing one-shot conversions using
the STANDBY command; the sequence for this is shown in
Figure 20. Issue the WAKEUP command from Standby
mode to begin a one-shot conversion. Following the settling
time (t
18
), DRDY will go low, indicating that the conversion is
complete and data can be read using the RDATA command.
The ADs1255/6 settles in a single cycle—there is no need to
ignore or discard data. Following the data read cycle, issue
another STANDBY command to reduce power consumption.
When ready for the next measurement, repeat the cycle
starting with another WAKEUP command.
Settling Time while Continuously Converting
After a synchronization, input multiplexer change, or
wakeup from Standby mode, the ADS1255/6 will
continuously convert the analog input. The conversions
coincide with the falling edge of DRDY. While continuously
converting, it is often more convenient to consider settling
times in terms of DRDY periods, as shown in Table 15.
The DRDY period equals the inverse of the data rate.
If there is a step change on the input signal while
continuously converting, performing a synchronization
operation to start a new conversion is recommended.
Otherwise, the next data will represent a combination of
the previous and current input signal and should therefore
be discarded. Figure 21 shows an example of readback in
this situation.
Table 15. Data Settling Delay vs Data Rate
DATA RATE
(SPS)
SETTLING TIME
(DRDY Periods)
30,000
5
15,000
3
7500
2
3750
1
2000
1
1000
1
500
1
100
1
60
1
50
1
30
1
25
1
15
1
10
1
5
1
2.5
1
DOUT
Settled
Data
STANDBY
WAKEUP
t
18
DRDY
DIN
ADS1255/6
Status
RDATA
Performing OneShot Conversion
Standby
Mode
Standby
Mode
STANDBY
Figure 20. One-Shot Conversions Using the STANDBY Command
DRDY
V
IN
= AIN
P
AIN
N
DIN
DOUT
Old V
IN
Data
Settled
Data
RDATA
Fully Settled
New V
IN
Data
Mix of
Old and New
V
IN
Data
Old V
IN
New V
IN
Figure 21. Step Change on V
IN
while Continuously Converting for Data Rates
≤
3750SPS
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| ADS1271EVM-PDK | modular EVM form factor |
| ADS1271EVM | modular EVM form factor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1256EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1256EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1256IDB | 制造商:BB 制造商全稱:BB 功能描述:Very Low Noise, 24-Bit Analog-to-Digital Converter |
| ADS1256IDBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1256IDBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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