參數(shù)資料
型號： ADS1256
英文描述： Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述： 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 20/39頁
文件大?。?/td> 427K
代理商： ADS1256
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
20
5.76MHz, 7.68MHz, are the same. The digital filter will
attenuate high-frequency noise on the ADS1255/6 inputs
up to the frequency where the response repeats. If
significant noise on the inputs is present above this
frequency, make sure to remove with external filtering.
Fortunately, this can be done on the ADS1255/6 with a
simple RC filter, as shown in the Applications Section (see
Figure 25).
0
20
40
60
80
100
120
140
G
0
1.92
3.84
5.76
7.68
Frequency (MHz)
f
D ATA
= 30kSPS
f
C LK IN
= 7.68MHz
Figure 16. Frequency Response Out to 7.68MHz
for Data Rate = 30kSPS
0
20
40
60
80
100
120
140
G
0
1.92
3.84
5.76
7.68
Frequency (MHz)
f
D ATA
= 2.5S PS
f
C L K IN
= 7.68MHz
Figure 17. Frequency Response Out to 7.68MHz
for Data Rate = 2.5SPS
SETTLING TIME
The ADS1255/6 features a digital filter optimized for fast
settling. The settling time (time required for a step change
on the analog inputs to propagate through the filter) for the
different data rates is shown in Table 13. The following
sections highlight the single-cycle settling ability of the
filter and show various ways to control the conversion
process.
Table 13. Settling Time vs Data Rate
DATA RATE
(SPS)
SETTLING TIME (t18)
(ms)
30,000
0.21
15,000
0.25
7500
0.31
3750
0.44
2000
0.68
1000
1.18
500
2.18
100
10.18
60
16.84
50
20.18
30
33.51
25
40.18
15
66.84
10
100.18
5
200.18
2.5
400.18
NOTE: fCLKIN = 7.68MHz.
Settling Time Using Synchronization
The SYNC/PDWN pin allows direct control of conversion
timing. Simply issue a Sync command or strobe the
SYNC/PDWN pin after changing the analog inputs (see
the Synchronization section for more information). The
conversion begins when SYNC/PDWN is taken high,
stopping the current conversion and restarting the digital
filter. As soon as SYNC/PDWN goes low, the DRDY
output goes high and remains high during the conversion.
After the settling time (t
18
), DRDY goes low, indicating that
data is available. The ADS1255/6 settles in a single
cycle—there is no need to ignore or discard data after
synchronization. Figure 18 shows the data retrieval
sequence following synchronization.
DRDY
AIN
P
AIN
N
DIN
DOUT
t
18
Settled
Data
RDATA
SYNC/PDWN
Figure 18. Data Retrieval After Synchronization
相關(guān)PDF資料
PDF描述
ADS1271 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER
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ADS1271EVM-PDK modular EVM form factor
ADS1271EVM modular EVM form factor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1256EVM 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1256EVM-PDK 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1256 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1256IDB 制造商:BB 制造商全稱:BB 功能描述:Very Low Noise, 24-Bit Analog-to-Digital Converter
ADS1256IDBR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1256IDBRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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