參數(shù)資料
型號: ADS1255IDBR
英文描述: Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述: 極低噪聲,24位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 15/39頁
文件大?。?/td> 427K
代理商: ADS1255IDBR
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
15
OPEN/SHORT SENSOR DETECTION
The sensor detect current sources (SDCS) provide a
means to verify the integrity of the external sensor
connected to the ADS1255/6. When enabled, the SDCS
supply a current (I
SDC
) of approximately 0.5
μ
A, 2
μ
A, or
10
μ
A to the sensor through the input multiplexer. The
SDCS bits in the ADCON register enable the SDCS and
set the value of I
SDC
.
When the SDCS are enabled, the ADS1255/6
automatically turns on the analog input buffer regardless
of the BUFEN bit setting. This is done to prevent the input
circuitry from loading the SDCS. AIN
P
must stay below 3V
to be within the absolute input range of the buffer. To
ensure this condition is met, a 3V clamp will start sinking
current from AIN
P
to AGND if AIN
P
exceeds 3V. Note that
this clamp is activated only when the SDCS are enabled.
Figure 7 shows a simplified diagram of ADS1255/6 input
structure with the external sensor modeled as resistance
R
SENS
between two input pins. When the SDCS are
enabled, they source I
SDC
to the input pin connected to
AIN
P
and sink I
SDC
from the input pin connected to AIN
N
.
The two 25
series resistors, R
MUX,
model the
ADS1255/6 internal resistances. The signal measured
with the SDCS enabled equals the total IR drop:
I
SDC
×
(2R
MUX
+ R
SENS
). Note that when the sensor is a
direct short (that is, R
SENS
= 0), there will still be a small
signal measured by the ADS1255/6 when the SDCS are
enabled: I
SDC
×
2R
MUX
.
NOTE: Arrows indicate switch positions when the SDCS are enabled.
AVDD
Input
Buffer
3V
Clamp
Sensor Detect
Current Source
Sensor Detect
Current Source
R
MUX
25
AIN
N
AIN
P
R
MUX
25
R
SENS
Figure 7. Sensor Detect Circuitry
ANALOG INPUT BUFFER
To dramatically increase the input impedance presented
by the ADS1255/6, the low-drift chopper-stabilized buffer
can be enabled via the BUFEN bit in the STATUS register.
The input impedance with the buffer enabled can be
modeled by a resistor, as shown in Figure 8. Table 7 lists
the values of Z
EFF
for the different data rate settings. The
input impedance scales inversely with the frequency of
CLKIN. For example, if f
CLKIN
is reduced by half to
3.84MHz, Z
EFF
for a data rate of 50SPS will double from
80M
to 160M
.
AINP
AINN
Input
Multiplexer
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
A
ZEFF
Figure 8. Effective Impedance with Buffer On
Table 7. Input Impedance with Buffer On
DATA RATE
(SPS)
ZEFF
(M
)
30,000
10
15,000
10
7,500
10
3,750
10
2,000
10
1,000
20
500
40
100
40
60
40
50
80
NOTE: fCLKIN = 7.68MHz.
With the buffer enabled, the voltage on the analog inputs
with respect to ground (listed in the Electrical
Characteristics as
Absolute Input Voltage
) must remain
between AGND and AVDD 2.0V. Exceeding this range
reduces performance, in particular the linearity of the
ADS1255/6. This same voltage range, AGND to
AVDD 2.0V, applies to the reference inputs when
performing a self gain calibration with the buffer enabled.
相關PDF資料
PDF描述
ADS1255IDBT Very Low Noise, 24-Bit Analog-to-Digital Converter
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