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參數(shù)資料
| 型號： | ADS1252K5 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 24位20kHz的，低功耗模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 131K |
| 代理商： | ADS1252K5 |
9
ADS1252
clock (CLK) (modulator clock = CLK
÷
6), the number of
system clocks required for the digital filter to fully settle is
5 64 6, or 1920 CLKs. This means that any significant
step change at the analog input requires five full conversions
to settle. However, if the analog input change occurs asyn-
chronously to the DOUT/DRDY pulse, six conversions are
required to ensure full settling.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1252.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed +V
D
.
Once the ADS1252 powers up, the DOUT/DRDY line will
pulse LOW on the first conversion. This data will not be
valid. The sixth pulse of DOUT/DRDY will be valid data
from the analog input signal.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready mode (DRDY) to indicate that new data has been
loaded into the data output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). The time domain partitioning of the DRDY
and DOUT function is shown in Figure 11.
The basic timing for DOUT/DRDY is shown in Figure 12.
During the time defined by t
2
, t
3
, and t
4
, the DOUT/DRDY
pin functions in DRDY mode. The state of the
DOUT/DRDY pin would be HIGH prior to the internal
transfer of new data to the DOR. The result of the A/D
conversion would be written to the DOR from MSB to LSB
in the time defined by t
1
(see Figures 11 and 12). The
DOUT/DRDY line would then pulse LOW for the time
defined by t
2
, and then pulse HIGH for the time defined by
t
3
to indicate that new data was available to be read. At this
point, the function of the DOUT/DRDY pin would change
SYMBOL
t
DRDY
DRDY Mode
DOUT Mode
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
DESCRIPTION
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
DOUT/DRDY LOW Time
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propogation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propogation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
MIN
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
384 CLK
36 CLK
348 CLK
6 CLK
6 CLK
6 CLK
24 CLK
30
30
30
5
30
30
3 CLK
1537 CLK
0.5 CLK
7679 CLK
6143.5 CLK
314.5 CLK
7681 CLK
591.5 CLK
592.5 CLK
6143.5 CLK
TABLE II. Digital Timing.
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
Frequency (Hz)
60
61
62
63
64
65
55
G
FIGURE 10. Expanded Digital Filter Response (60Hz with
a 10Hz Notch).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
Frequency (Hz)
60
61
62
63
64
65
55
G
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| ADS1252U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC 41.7KSPS SMD |
| ADS1252U/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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