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參數(shù)資料
| 型號： | ADS1245 |
| 英文描述： | Low-Power, 24-Bit Analog-to-Digital Converter |
| 中文描述： | 低功耗，24位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 254K |
| 代理商： | ADS1245 |
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SBAS287A JUNE 2003 REVISED SEPTEMBER 2003
www.ti.com
9
To help see the response at lower frequencies, Figure 19
illustrates the response out to 180Hz. Notice that both
50Hz and 60Hz signals are rejected. This feature is very
useful for eliminating power line cycle interference during
measurements. Figure 20 shows the ADS1245 response
around these frequencies.
Frequency (Hz)
G
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
0
20
40
60
80
100
120
140
160
180
f
CLK
= 2.4576MHz
Figure 19. Frequency Response to 180Hz
Frequency (Hz)
G
50
55
60
65
45
40
50
60
70
80
90
100
110
120
f
CLK
= 2.4576MHz
Figure 20. Frequency Response Near
50Hz and 60Hz
The ADS1245 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2.4576MHz to 4.9152MHz, the data rate
increases from 15sps to 30sps while the notches in the
response at 50Hz and 60Hz move out to 100Hz and
120Hz.
SETTLING TIME
The ADS1245 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving
the data when there is a change on the analog inputs.
I
n order to realize single-cycle settling, synchronize
changes on the analog inputs to the conversion beginning,
which is indicated by the falling edge of DRDY/DOUT. For
example, when using a multiplexer in front of the
ADS1245,
change
the
DRDY/DOUT goes low. Increasing the time between the
conversion beginning and the change on the analog inputs
(t
DELAY
) results in a settling error in the conversion data, as
shown in Figure 21. The settling error versus delay time is
shown in Figure 22. If the input change is delayed to the
point where the settling error is too high, simply ignore the
first data result and wait for the second conversion, which
will be fully settled.
multiplexer
inputs when
Delay Time, t
DELAY
(ms)
S
2
4
6
8
10
12
14
16
0
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
f
CLK
= 2.4576MHz
Figure 21. Settling Error vs Delay Time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS1245IDGSR | Low-Power, 24-Bit Analog-to-Digital Converter |
| ADS1245IDGST | Low-Power, 24-Bit Analog-to-Digital Converter |
| ADS1250 | 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER |
| ADS1250U | 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER |
| ADS1252 | 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1245IDGSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGSRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGST | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGST | 制造商:Texas Instruments 功能描述:IC 24-BIT ADC HIGH-Z I/P BUFFER |
| ADS1245IDGSTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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