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參數(shù)資料
| 型號(hào)： | ADS1245 |
| 英文描述： | Low-Power, 24-Bit Analog-to-Digital Converter |
| 中文描述： | 低功耗，24位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 254K |
| 代理商： | ADS1245 |
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SBAS287A JUNE 2003 REVISED SEPTEMBER 2003
www.ti.com
11
DATA FORMAT
The ADS1245 outputs 24 bits of data in Binary Two’s
Complement format. The least significant bit (LSB) has a
weight of (2V
REF
)/(2
23
1). A positive full-scale input
produces an output code of 7FFFFFh and the negative
full-scale input produces an output code of 8000000h. The
output clips at these codes for signals exceeding
full-scale. Table 1 summarizes the ideal output codes for
different input signals.
Table 1. Ideal Output Code vs Input Signal
INPUT SIGNAL V
IN
(AINP AINN)
≥
+2V
REF
2V
REF
(2
23)
0
IDEAL OUTPUT CODE
(1)
7FFFFF
H
000001
H
1
000000
H
FFFFFF
H
2V
REF
(2
23)
1
2V
REF
2
23
(2
23)
1
800000
H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
DATA RETRIEVAL
The ADS1245 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes low,
as shown in Figure 24. After this occurs, begin shifting out
the data by applying SCLKs. Data is shifted out most
significant bit (MSB) first. It is not required to shift out all the
24 bits of data, but the data must be retrieved before the
new data is updated (see t
3
) or else it will be overwritten.
Avoid data retrieval during the update period.
DRDY/DOUT remains at the state of the last bit shifted out
until it is taken high (see t
7
), indicating that new data is
being updated.
To avoid having DRDY/DOUT remain in the state of the
last bit, shift a 25th SCLK to force DRDY/DOUT high; see
Figure 25. This technique is useful when a host controlling
the ADS1245 is polling DRDY/DOUT to determine when
data is ready.
DRDY/DOUT
23
22
21
1
24
0
LSB
MSB
Data
Datais ready.
SCLK
t
3
t
8
t
4
t
4
t
7
New data is ready.
t
5
t
6
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
(1) Load on DRDY/DOUT = 20pF||100k
.
(2) Values given for f
= 2.4576MHz. For different CLK frequencies, scale
proportional to CLK period. For example, for f
CLK
= 4.9152MHz, t
8
→
33.333ms.
t
3
t
4
t
5
(1)
t
6
t
7
t
8
(2)
DRDY/DOUT low to first SCLK rising edge.
SCLK positive or negative pulse width.
SCLK rising edge to new data bit valid;
propagation delay.
SCLK rising edge to old data bit valid: hold time.
Data updating, no read back allowed.
Conversion time (1/data rate).
0
100
50
0
152
66.667
152
66.667
ns
ns
ns
ms
ns
μ
s
NOTES:
Figure 24. Data Retrieval Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1245IDGSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGSRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGST | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGST | 制造商:Texas Instruments 功能描述:IC 24-BIT ADC HIGH-Z I/P BUFFER |
| ADS1245IDGSTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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