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參數(shù)資料
| 型號： | ADS1244IDGST |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC LP 24-BIT 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 270µW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 889 (CN2011-ZH PDF) |
| 配用： | 296-18359-ND - EVALUATION MODULE FOR ADS1244 |
| 其它名稱： | 296-14003-6 |
ADS1244
12
SBAS273
www.ti.com
FIGURE 14. Self-Calibration Timing.
23
DRDY/DOUT
SCLK
124
t
9
25
26
23
22
21
0
Data ready after cal.
Cal begins.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t9(1)
First data ready after calibration.
209
210
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
SELF-CALIBRATION
The user can initiate self-calibration at any time, though in
many applications the ADS1244’s drift performance is good
enough that the self-calibration performing automatically at
power-up is all that is needed. To initiate a self-calibration,
apply at least two additional SCLKs after retrieving 24 bits of
data. Figure 14 shows the timing pattern. The 25th SCLK will
send DRDY/DOUT HIGH. The falling edge of the 26th SCLK
will begin the calibration cycle. Additional SCLK pulses may
be sent after the 26th SCLK, but try to minimize activity on
SCLK during calibration for best results.
When the calibration is complete, DRDY/DOUT will go LOW
indicating that new data is ready. There is no need to alter the
analog input signal applied to the ADS1244 during calibration,
the inputs pins are disconnected within the A/D converter and
the appropriate signals applied internally automatically. The
first conversion after a calibration is fully settled and valid for
use. The time required for a calibration depends on two
independent signals: the falling edge of SCLK and an internal
clock derived from CLK. Variations in the internal calibration
values will change the time required for calibration (t9) within
the range given by the MIN/MAX specs. t12 and t13 described
in the next section are affected likewise.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1244IDGSTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245 | 制造商:BB 制造商全稱:BB 功能描述:Low-Power, 24-Bit Analog-to-Digital Converter |
| ADS1245IDGSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGSRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGST | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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