參數(shù)資料
型號(hào)： ADS1244IDGST
廠商： Texas Instruments
文件頁(yè)數(shù)： 23/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC LP 24-BIT 10-MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 270µW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 889 (CN2011-ZH PDF)
配用： 296-18359-ND - EVALUATION MODULE FOR ADS1244
其它名稱： 296-14003-6
ADS1244
8
SBAS273
www.ti.com
VOLTAGE REFERENCE INPUTS (VREFP, VREFN)
The voltage reference used by the modulator is generated
from the voltage difference between VREFP and VREFN:
VREF = VREFP – VREFN. The reference inputs use a structure
similar to that of the analog inputs. A simplified diagram of the
circuitry on the reference inputs is shown in Figure 5. The
switches and capacitors can be modeled with an effective
impedance =
t
pF
SAMPLE
2
25
/
= 1M
for f
CLK = 2.4576MHz.
Minimize the overshoot and undershoot on CLK for the best
analog performance. A small resistor in series with CLK (10
to 100
) can often help. CLK can be generated from a number
of sources including stand-alone crystal oscillators and
microcontrollers. The MSP430, an ultra low power
microcontroller, is especially well suited for this task. Using the
MSP430’s FLL clock generator available on the 4xx family, it’s
easy to produce a 2.4576MHz clock from a 32.768kHz crystal.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. It indicates when
new data is ready by going LOW. Afterwards, on the first rising
edge of SCLK, the DRDY/DOUT pin changes function and
begins outputting the conversion data, MSB first. Data is
shifted out on each subsequent SCLK rising edge. After all 24
bits have been retrieved, the pin can be forced HIGH with an
additional SCLK. It will then stay HIGH until new data is ready.
This is useful when polling on the status of DRDY/DOUT to
determine when to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising edge.
As with CLK, this input may be driven with 5V logic regard-
less of the DVDD or AVDD voltage. There is hysteresis built
into this input, but care should still be taken to ensure a clean
signal. Glitches or slow rising signals can cause unwanted
additional shifting. For this reason, it is best to make sure the
rise-and-fall times of SCLK are less than 50ns.
FREQUENCY RESPONSE
The ADS1244’s frequency response for fCLK = 2.4576MHz is
shown in Figure 6. The frequency response repeats at mul-
tiples of 19.2kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 13.7Hz. As can be seen,
the ADS1244 does a good job attenuating out to 19kHz. For
the best resolution, limit the input bandwidth to below this value
to keep higher frequency noise from affecting performance.
Often a simple RC filter on the ADS1244’s analog inputs is all
that is needed.
FIGURE 5. Simplified Reference Input Circuitry.
25pF
S
2
S
1
S
1
AVDD
VREFP
VREFN
AVDD
ESD
Protection
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages on
the reference pins do not go below GND by more than
100mV, and likewise do not exceed AVDD by 100mV:
GND – 100mV < (VREFP, VREFN) < AVDD + 100mV.
VREF is typically AVDD/2, but it can be raised as high as
AVDD. When VREF exceeds AVDD/2, it will not be possible
to reach the full-scale digital output value corresponding to
±2V
REF since this would require the analog inputs to exceed
the power supplies. For example, if VREF = AVDD = 5V, the
positive full-scale signal is 10V. The maximum positive input
signal that can be supplied before the ESD diodes begin to turn
on is when AINP = 5.1V and AINN = –0.1V
→ V
IN = 5.2V.
Therefore, it will not be possible to reach the positive (or
negative) full-scale readings in this configuration. The digital
output codes will be limited to approximately one half of the
entire range.
For best performance, bypass the voltage reference inputs
with a 0.1
F capacitor between VREFP and VREFN. Place
the capacitor as close as possible to the pins.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the ADS1244.
The recommended CLK frequency is 2.4576MHz. This places
the notches of the digital filter at 50Hz and 60Hz and sets the
data rate at 15SPS. The CLK frequency can be increased to
speed up the data rate, but the frequency notches will move
in frequency proportionally. CLK must be left running during
normal operation. It may be turned off during Sleep Mode to
save power, but this is not required. The CLK input may be
driven with 5V logic, regardless of the DVDD or AVDD voltage.
FIGURE 6. Frequency Response.
FREQUENCY RESPONSE
f
CLK = 2.4576MHz
Frequency (kHz)
Gain
(dB)
9.6
19.2
0
–20
–40
–60
–80
–100
–120
–140
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1244IDGSTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1245 制造商:BB 制造商全稱:BB 功能描述:Low-Power, 24-Bit Analog-to-Digital Converter
ADS1245IDGSR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1245IDGSRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1245IDGST 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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