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參數(shù)資料
| 型號(hào)： | ADRF6704ACPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | 2500 MHz - 2900 MHz RF/MICROWAVE I/Q MODULATOR |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP_VQ, CP-40-1, 40 PIN |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 581K |
| 代理商： | ADRF6704ACPZ |
Preliminary Technical Data
ADRF6704
Table 5. Pin Function Descriptions
Pin Nr.
Mnemonic
Description
1,10,17,22,
VDD
Power Supply: Power supply voltage range is 4.75 V to 5.25 V. Each pin should be decoupled with a 100 pf and
27,29,34
0.1uF capacitors located close to the pin.
2,9, 40
DECL
Internal Decoupling Nodes: Connect a 100 pF and a 0.1uF capacitor between each of these pins and ground.
3
CP
Charge Pump: Chargepump Output Pin. Connect to VTUNE through loop filter
4, 7,11,15,20,
GND
Ground: Connect these pins to a low impedance ground planeGND
21,23,24,25,2
8,30,31,35
5
RSET
Charge Pump Current: The nominal charge pump current can be set to either 250 uA, 500 uA, 750 uA or 1 mA
using DB10 and DB11 of Register 4 and by setting DB18 to 0 (Internal Reference Current). In this mode, no external
RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked
according to the equation.
[]
37 .8
250
217 .4
,
×
Ω =
CP BASE
SET
I
R
Where ICP,BASE is the base charge pump current in μA. For further details on the charge pump current, see Register 4
- Charge Pump, PFD and Reference Path Control.
6
REFIN
Refence Input: Nominal input level is 1Vpp. Input range is 10 MHz to 160 MHz.
8
MUXOUT
Multiplexer Output: This output can be programmed to provide the Reference Output signal or the Lock Detect
signal. The output is selected by programming the appropriate register.
12
DATA
Serial Data Input: The serial data input is loaded MSB first with the three LSBs being the control bits.
13
CLK
Serial Clock Input: This serial clock input is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14
LE
Load Enable: When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six
registers, the relevant latch being selected by the first three control bits of the 24-bit word.
16
ENOP
Modulator Output Enable/Disable
ENOP
R5:DB6
Output
X
0
DISABLED
0
X
DISABLED
1
ENABLED
18,19, 32,33
QP, QN, IN,
Modulator Baseband Inputs: Differential In-Phase and Quadrature Baseband Inputs. These high impedance
IP
inputs should be dc-biased to 0.5 V.
26
RFOUT
RF Output: Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to its load.
36
LOSEL
LO Select: This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and
LON become inputs if the LOSEL pin is set low AND the LDRV bit of Register 5 is set low. External LO drive must be a
2XLO. In addition to setting LOSEL and LDRV low and providing an external 2XLO, the LXL bit of Register 5 (DB4)
must be set to 1 to direct the external LO to the IQ Modulator. LON and LOP become outputs when LOSEL is high
OR if the LDRV bit of Register 5 (DB3) is set high. A 1X or 2X LO output can be selected by setting the LDIV bit of
Register 5 (DB5) to 1 or 0 respectively.
LON/LOP Function
LOSEL
R5:DB3 (LDRV)
R5:DB5(LDIV)
R5:DB4(LXL)
Input (2XLO)
0
X
1
Output (1XLO)
X
1
0
X
Output (1XLO)
1
X
0
X
Output (2XLO)
X
1
X
Output (2XLO)
1
X
1
X
X = Don’t Care
LOSEL should not be left floating.
37,38
LON, LOP
Local Oscillator Input/Output: The internally generated 1XLO or 2XLO is available on these pins.
When internal LO generation is disabled, an external 1XLO or 2XLO can be applied to these pins.
39
VTUNE
VCO Control Voltage Input: This pin is driven by the output of the loop filter. Nominal input voltage range on this
pin is 1.5 V to 2.5 V
EP
Exposed Paddle: The exposed paddle should be soldered to a low impedance ground plane.
Rev. PrE | Page 7 of 18
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