參數(shù)資料
型號(hào)： ADP5589ACPZ-02-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 0K
描述： IC KEY DECODER 19I/O EXP 24LFCSP
標(biāo)準(zhǔn)包裝： 1,500
應(yīng)用： 小鍵盤輸入，輸入/輸出擴(kuò)展
接口： I²C
電源電壓： 1.65 V ~ 3.6 V
封裝/外殼： 24-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-WQ（3.5x3.5）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Data Sheet
ADP5589
Rev. B | Page 41 of 52
RESET1_EVENT_C Register 0x3A
Table 66. RESET1_EVENT_C Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the third reset event should be.
[6: 0]
RESET1_EVENT_C[6:0]
R/W
Defines an event that can be used to generate the RESET1 signal.
RESET2_EVENT_A Register 0x3B
Table 67. RESET2_EVENT_A Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the first reset event should be.
For key events:
0 = not applicable; releases not used for reset generation.
1 = press is used as reset event.
For GPIs and logic outputs configured for FIFO updates:
0 = inactive event used as reset condition.
1 = active event used as reset condition.
[6:0]
RESET2_EVENT_A[6:0]
R/W
Defines an event that can be used to generate the RESET2 signal.
Up to two events can be defined for generating the RESET2 signal, using
RESET2_EVENT_A[6:0] and RESET2_EVENT_B[6:0].
If one of the registers is 0, that register is not used for reset generation. All reset events
must be detected at the same time to trigger the reset.
RESET2_EVENT_B Register 0x3C
Table 68. RESET2_EVENT_B Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the second reset event should be.
[6:0]
RESET2_EVENT_B[6:0]
R/W
Defines an event that can be used to generate the RESET2 signal.
RESET_CFG Register 0x3D
Table 69. RESET_CFG Bit Descriptions
Bits
Name
R/W
Description
7
RESET2_POL
R/W
Sets the polarity of RESET2.
0 = RESET2 is active low.
1 = RESET2 is active high.
6
RESET1_POL
R/W
Sets the polarity of RESET1.
0 = RESET1 is active low.
1 = RESET1 is active high.
5
RST_PASSTHRU_EN
R/W
Allows the RST pin to override (OR with) the RESET1signal.
Function not applicable to RESET2.
[4:2]
RESET_TRIGGER_TIME[2:0]
R/W
Defines the length of time that the reset events must be active before a reset signal is
generated.
All events must be active at the same time for the same duration. Parameter common
to both RESET1 and RESET2.
000 = immediate.
001 = 1.0 sec.
010 = 1.5 sec.
011 = 2.0 sec.
100 = 2.5 sec.
101 = 3.0 sec.
110 = 3.5 sec.
111 = 4.0 sec.
相關(guān)PDF資料
PDF描述
V110B48H150BL2 CONVERTER MOD DC/DC 48V 150W
ADP5589ACBZ-00-R7 IC PORT EXPANDER 19I/O 25WLSCP
V110B48H150B3 CONVERTER MOD DC/DC 48V 150W
ADP5589ACBZ-01-R7 IC PORT EXPANDER 19I/O 25WLSCP
PIC12F675-I/MF IC MCU CMOS 1K FLASH W/AD 8-DFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADP5589CP-EVALZ 功能描述:BOARD EVAL ADP5589ACPZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
ADP-5DB 制造商:Delta Power 功能描述:
ADP-5DB-A 制造商:Delta Electronics Inc 功能描述:
ADP-5DBAB 制造商:Delta Electronics Inc 功能描述:
ADP-5JB-A 制造商:Delta Electronics Inc 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*