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參數(shù)資料
| 型號： | ADP3810AR-168 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector Cable Assembly; Connector Type A:Circular Plug; Connector Type B:Stripped End Leads; Cable Length:10ft; Features:500 Mating Cycles, PVC Jacket, IP67 Rating, E63093 Rated Connector; No. of Contacts:3 RoHS Compliant: Yes |
| 中文描述： | 二次側(cè)，離線電池充電器控制器 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 457K |
| 代理商： | ADP3810AR-168 |
ADP3810/ADP3811
–15–
REV. 0
Step 9. Iterate C
C1
:
Because f
Z1
is very close to f
CV
, it will increase the error ampli-
fier gain in a nonnegligible amount at the 0 dB point. The in-
crease in gain is calculated as:
20
×
log 1
+
f
Z
1
f
CV
2
=
7.1
dB
Now, the total error amplifier gain loss required is:
G
LOSS
= 37.6
dB
+ 7.1
dB
= 44.7
dB
With this, the new f
P1
can be calculated from the equation in
Step 5.
f
P
1
= 0.58
Hz
Finally, C
C1
is recalculated using the equation in Step 6.
C
C
1
=
1
2
π×
400
k
×
0.58
Hz
≈
0.7
μ
F
Following these steps gives a cookbook method for calculating
the compensation components for the voltage loop. As men-
tioned above, these components can be optimized in the actual
circuit. The results of a PSpice
1
analysis of the loop is shown in
Figure 32. The open loop gain of the loop is 108 dB as calcu-
lated. The crossover frequency is 100 Hz with a phase margin
of 52
°
. The graph shows the phase leveling off at 90
°
. In reality
the phase will continue to fall as higher frequency parasitic poles
take effect.
1
PSpice is a trademark of MicroSim Corporation.
FREQUENCY – Hz
–100
P
0.01
100k
0.1
1
10
100
200
100
0
0
180
90
G
1k
0dB CROSSOVER
PHASE MARGIN = 52
Figure 32. Voltage Loop Gain/Phase Plots
Voltage Loop Compensation, Battery Present
When the battery has finished charging and is still connected to
the charging circuitry, the system is said to be “floating” the bat-
tery. The loop is maintaining a constant output voltage equal to
the battery voltage, and the output current has dropped to
nearly zero. This case is actually the easiest to compensate be-
cause the battery’s capacitance creates a very low frequency
dominant pole, giving a single pole response. For example, if the
battery is modeled as a 10 Farad capacitor, the dominant pole
will be 1/(2
π
×
1.2 k
×
10 F) = 0.013 MHz. This very low fre-
quency pole causes the system to cross over 0 dB at less than
10 Hz, giving a stable single pole system. The compensation
components have little effect on this response, so no further
calculations are needed for this case.
Current Loop Compensation
Now that the voltage loop compensation is complete, it is time
to add the compensation for the current loop. The definitions
for modulator gain and error amplifier gain are the same as be-
fore; but now, the controlling error amplifier is GM1 in Figure
31, as opposed to GM2, for the voltage loop. Otherwise, the
calculations are very similar.
Step 10. Calculate the dc loop gain (G
LOOP
), f
PM
, and f
ZM
:
[
G
MOD
=
20
×
log
GM
3
×
ITX
OC
×
R
F
×
A
V
2
×
GM
4
×
R
CS
]
G
MOD
=
20
×
log
6
mA
/
V
×
0.36
×
3.3
k
×
0.333
×
1.0
A
/
V
×
0.25
4.5
dB
G
EA
=
20
×
log
GM
1
×
R
5
8.3
mA
/
V
×
400
k
[
[
]
=
20log
]
=
70.4
dB
G
LOOP
= –6.1
dB
+ 70.4
dB
= 64.3
dB
f
PM
=
1
2
π×
R
CS
+
R
F
1
(
)
×
C
F
1
=
1
2
π×
0.35
×
1
mF
=
450
Hz
f
ZM
=
1
2
π×
R
F
1
×
C
F
1
=
1
2
π×
0.1
×
1
mF
=
1.6
kHz
Step 11. Pick the current loop crossover frequency, f
CI
:
From Step 2 in the voltage loop calculations, f
CI
~ 1.9 kHz.
Step 12. Calculate G
MOD
at f
CI
:
The modulator gain of –4.5 dB is the dc gain. The modulator
pole reduces this gain above f
PM
.
G
MOD
=
1.9
kHz
(
)
=
G
MOD
dc
( )
20
×
log 1
+
f
CI
f
PM
2
+
20
×
log 1
+
f
CI
f
ZM
2
G
MOD
=
1.9
kHz
If the 1 mF capacitor has a much higher ESR, e.g., 1
, the
modulator zero, f
ZM
, will be lower in frequency than the modu-
lator pole, f
PM
. This causes the loop gain and bandwidth to in-
crease and could cause instability. One possible solution to this
scenario is to use a much higher value (47 nF) for the C
F
= 1 nF
capacitor. The pole of this capacitor would then be in the 1 kHz
range and would reduce the loop gain. If the ESR is much less
than 0.1
, the bandwidth of the loop will decrease slightly.
Step 13. Calculate gain loss of G
EA
at f
CI
:
The gain loss of G
EA
in the current loop is a combination of the
loss due to C
C1
, R
C1
and the additional loss from C
C2
, R
C2
. To
calculate the contribution of gain roll-off needed from C
C2
, R
C2
,
the effective gain of G
EA
must first be calculated. Since the gain
is calculated at 1.9 kHz, the impedance of C
C1
is 120
. Thus,
the gain becomes:
(
(
(
)
=
4.5
dB
12.7
dB
+
3.8
dB
=
–13.4
dB
G
EA
1.9
kHz
G
EA
1.9
kHz
G
LOSS
=
G
EA
(1.9
kHz
) –
G
MOD
(1.9
kHz
)
= 38.9
dB
– 13.4
dB
= 25.5
dB
)
=
20
×
log
GM
1
×
R
6
+
R
C
1
+
120
)
=
20
×
log 8.3
mA
/
V
×
10320
(
)
[
]
(
)
]
=
38.9
dB
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