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參數(shù)資料
| 型號： | ADP3808JCPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | High Efficiency Switch Mode Li-Ion Battery Charger |
| 中文描述： | BATTERY CHARGE CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, QCC24 |
| 封裝： | ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 315K |
| 代理商： | ADP3808JCPZ-RL |
ADP3808
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 16
ISYS
1
LIMSET
2
LIMIT
3
EXTPWR
4
DRVREG
18
DRVL
17
PGND
16
RT
5
CSP
15
CSM
14
REFIN
6
CSADJ
13
B
7
E
8
C
9
A
S
2
S
2
V
2
B
S
2
D
2
C
B
1
0
ADP3808
TOP VIEW
(Not to Scale)
Figure 2. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1
ISYS
2
LIMSET
3
LIMIT
4
EXTPWR
Description
Output for System Current Sense Amplifier.
System Current Limit Set Point Input.
System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum of 6 V.
External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is present. A pull-up
resistor is required to a maximum of 6 V.
Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets the oscillator
frequency of the device.
Reference Input for BATADJ and CSADJ.
Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program voltage from 4.0 V to
4.5 V per cell.
Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the circuitry
powered by V
CC
into a low power state. The system amplifier and EXTPWR are still active.
Output of Error Amplifiers and Compensation Point.
Analog Ground. Reference point for the battery sense and all analog functions.
Battery Sense Input.
Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell operation.
Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program the battery
charge current. (V
CSP
V
CSM
) = 96 mV x CSADJ/REFIN.
Negative Current Sense Input. This pin connects to the battery side of the battery current sense resistor.
Positive Current Sense Input. This pin connects to the inductor side of the battery current sense resistor.
Power Ground. This pin should closely connect to the source of the lower MOSFET.
Synchronous Rectifier Drive. Output drive for the lower MOSFET.
Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide filtering for the
low-side supply.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
Main Switch Drive. Output drive for the upper MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper MOSFET,
and is the floating return for the upper MOSFET drive signal.
Input Supply. This pin does not power the SYS amplifier section.
Negative System Current Sense Input. This pin connects to the battery side of the system current sense resistor.
Positive System Current Sense Input. This pin connects to the adapter side of the system current sense resistor.
This pin also provides power to the system amplifier section.
This pin should be connected to AGND.
5
RT
6
7
REFIN
BATADJ
8
EN
9
10
11
12
13
COMP
AGND
BAT
CELLSEL
CSADJ
14
15
16
17
18
CSM
CSP
PGND
DRVL
DRVREG
19
BST
20
21
DRVH
SW
22
23
24
VCC
SYSM
SYSP
25
Paddle
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