參數(shù)資料
型號(hào): ADP3418KRZ1
廠商: Analog Devices, Inc.
英文描述: Dual Bootstrapped 12 V MOSFET Driver with Output Disable
中文描述: 12伏雙自舉MOSFET驅(qū)動(dòng)器與輸出禁用
文件頁(yè)數(shù): 1/16頁(yè)
文件大小: 323K
代理商: ADP3418KRZ1
Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3418
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
1 PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float the
output per Intel VRM 10 and AMD Opteron specifications
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
Rev.
B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
www.analog.com
GENERAL DESCRIPTION
The ADP3418 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated, synchronous, buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 30 ns transition
time. One of the drivers can be bootstrapped, and is designed to
handle the high voltage slew rate associated with floating high-
side gate drivers. The ADP3418 includes overlapping drive
protection to prevent shoot-through current in the external
MOSFETs. The OD pin shuts off both the high-side and the
low-side MOSFETs to prevent rapid output capacitor discharge
during system shutdowns.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C, and is available in an 8-lead SOIC
package.
FUNCTIONAL BLOCK DIAGRAM
0
R
S
Q
Q
CMP
1V
VCC
6
DELAY
DELAY
5
7
CMP
2
3
OD
4
ADP3418
C
VCC
BST
VCC
DRVH
SW
DRVL
PGND
IN
6
1
C
BST1
R
BST1
8
R
G
C
BST2
D1
TO
INDUCTOR
Q1
Q2
12V
Figure 1.
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