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參數(shù)資料
| 型號(hào)： | ADN2819ACPZ-CML |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
ADN2819
Rev. B | Page 20 of 24
DC-COUPLED APPLICATION
The inputs to the ADN2819 can also be dc-coupled. This may
be necessary in burst mode applications where there are long
periods of CIDs and baseline wander cannot be tolerated. If the
inputs to the ADN2819 are dc-coupled, care must be taken not
to violate the input range and common-mode level
requirements of the ADN2819 (see Figure 26, Figure 27, and
Figure 28). If dc-coupling is required, and the output levels of
the TIA do not adhere to the levels shown in Figure 27 and
Figure 28, there needs to be level shifting and/or an attenuator
between the TIA outputs and the ADN2819 inputs.
LOL TOGGLING DURING LOSS OF INPUT DATA
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2819 will
stay within 1000 ppm of the VCO center frequency as long as
there is a valid reference clock. The LOL pin toggles at a rate of
several kHz because the LOL pin toggles between a Logic 1 and
a Logic 0, while the frequency loop and phase loop swap control
of the VCO. The chain of events is as follows:
The ADN2819 is locked to the input data stream; LOL = 0.
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
The phase loop tries to acquire, but there is no input data
present so the VCO frequency drifts.
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency loop.
This process is repeated until a valid input data stream is
re-established.
50
50
ADN2819
0.1
F
NIN
PIN
50
TIA
VREF
VCC
50
02999-B
-026
Figure 26. ADN2819 with DC-Coupled Inputs
VCM = 0.4V MIN
(DC-COUPLED)
VSE = 5mV MIN
PIN
NIN
V p-p = PIN – NIN = 2
× V
SE = 10mV AT SENSITIVITY
INPUT (V)
02999-
B-
027
Figure 27. Minimum Allowed DC-Coupled Input Levels
INPUT (V)
PIN
NIN
VCM = 0.6V
(DC-COUPLED)
VSE = 1.2V MAX
V p-p = PIN – NIN = 2
× V
SE = 2.4V MAX
02999-
B-
028
Figure 28. Maximum Allowed DC-Coupled Input Levels
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACPZ-CML-RL | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2820 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 制造商:Analog Devices 功能描述: |
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