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參數(shù)資料
型號: ADN2811ACPZ-CML
廠商: Analog Devices Inc
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC CLK/DATA REC W/AMP 48-LFCSP
標準包裝: 1
類型: 時鐘和數(shù)據(jù)恢復(CDR),多路復用器
PLL:
主要目的: SONET/SDH,STM
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.66GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP
包裝: 托盤
ADN2811
Rev. B | Page 4 of 20
Parameter
Conditions
Min
Typ
Max
Unit
Setup Time
TS (See Figure 3) OC-48
140
ps
Hold Time
TH (See Figure 3) OC-48
150
ps
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
@ REFCLKP or REFCLKN
0
VCC
V
Peak-to-Peak Differential Input
100
mV
Common-Mode Level
DC-Coupled, Single-Ended
VCC/2
V
TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N)
CML Inputs
Peak-to-Peak Differential Input Voltage
0.8
V
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
VIL
0.8
V
Input Current
VIN = 0.4 V or VIN = 2.4 V
5
+5
A
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
VOH, IOH = 2.0 mA
2.4
V
Output Low Voltage
VOL, IOL = +2.0 mA
0.4
V
1 PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
2 PWD measurement made on quantizer outputs in Bypass mode.
3 Measurement is equipment limited.
4 TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
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