參數(shù)資料
型號(hào): ADG714
廠商: Analog Devices, Inc.
英文描述: CMOS, Low Voltage Serially-Controlled, Octal SPST Switches
中文描述: 的CMOS低電壓串行控制,八SPST開(kāi)關(guān)
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 173K
代理商: ADG714
ADG714/ADG715
–5–
REV. 0
ADG714 TIMING CHARACTERISTICS
1, 2
Parameter
Limit at T
MIN
, T
MAX
30
33
13
13
0
5
4.5
0
33
20
Unit
Conditions/Comments
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
93
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time
SCLK Rising Edge to DOUT Valid
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
C
L
= 20 pF, R
L
= 1 k
.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DOUT
t
8
t
4
t
6
t
5
t
2
t
3
t
1
t
7
t
9
DB0
DB7
DB7
1
DB6
1
DB2
1
DB1
1
DB0
1
NOTE
1
DATA FROM PREVIOUS WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40 C to +85 C unless otherwise noted.)
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