參數(shù)資料
型號： ADG714
廠商： Analog Devices, Inc.
英文描述： CMOS, Low Voltage Serially-Controlled, Octal SPST Switches
中文描述： 的CMOS低電壓串行控制，八SPST開關
文件頁數(shù)： 2/16頁
文件大?。?/td> 173K
代理商： ADG714
–2–
REV. 0
ADG714/ADG715–SPECIFICATIONS
(V
DD
= 5 V 10%, V
SS
= 0 V, GND = 0 V unless otherwise noted)
B Version
–40 C
Parameter
+25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
0 V to V
DD
V
2.5
4.5
typ
max
typ
max
typ
max
V
S
= 0 V to V
DD
, I
S
= 10 mA
5
0.4
0.8
On-Resistance Match Between Channels (
R
ON
)
V
S
= 0 V to V
DD
, I
S
= 10 mA
V
S
= 0 V to V
DD
, I
S
= 10 mA
On-Resistance Flatness (R
FLAT(ON)
)
0.6
1.2
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
V
DD
= 5.5 V
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V
±
0.01
±
0.1
±
0.01
±
0.1
±
0.01
±
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
±
0.3
Drain OFF Leakage I
D
(OFF)
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V
±
0.3
Channel ON Leakage I
D
, I
S
(ON)
V
D
= V
S
= 1 V, or 4.5 V
±
0.3
DIGITAL INPUTS (SCLK, DIN,
SYNC
, A0, A1)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
2.4
0.8
V min
V max
μ
A typ
μ
A max
pF typ
0.005
V
IN
= V
INL
or V
INH
±
0.1
C
IN
, Digital Input Capacitance
2
DIGITAL OUTPUT ADG714 DOUT
2
Output Low Voltage
C
OUT
Digital Output Capacitance
DIGITAL INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
3
0.4
max
pF typ
I
SINK
= 6 mA
4
0.7 V
DD
V
+ 0.3
–0.3
0.3 V
DD
V min
V max
V min
V max
μ
A typ
μ
A max
V min
pF typ
Input Low Voltage, V
INL
I
IN
, Input Leakage Current
0.005
V
IN
= 0 V to V
DD
±
1
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage
0.05 V
DD
6
0.4
0.6
V max
V max
I
SINK
= 3 mA
I
SINK
= 6 mA
DYNAMIC CHARACTERISTICS
2
t
ON
ADG714
20
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
V
S
= 3 V, R
L
= 300
, C
L
= 35 pF
32
t
ON
ADG715
95
V
S
= 3 V, R
L
= 300
, C
L
= 35 pF
140
t
OFF
ADG714
8
V
S
= 3 V, R
L
= 300
, C
L
= 35 pF
15
t
OFF
ADG715
85
V
S
= 3 V, R
L
= 300
, C
L
= 35 pF
130
Break-Before-Make Time Delay, t
D
8
V
S
= 3 V, R
L
= 300
, C
L
= 35 pF
1
Charge Injection
Off Isolation
±
3
–60
–80
–70
–90
155
11
11
22
V
S
= 2 V, R
S
= 0
, C
= 1 nF
R
L
= 50
, C
L
= 5 pF, f = 10 MHz
R
L
= 50
, C
L
= 5 pF, f = 1 MHz
R
L
= 50
, C
L
= 5 pF, f = 10 MHz
R
L
= 50
, C
L
= 5 pF, f = 1 MHz
R
L
= 50
, C
L
= 5 pF
Channel-to-Channel Crosstalk
–3 dB Bandwidth
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
POWER REQUIREMENTS
I
DD
V
= 5.5 V
Digital Inputs = 0 V or 5.5 V
10
μ
A typ
μ
A max
20
NOTES
1
Temperature range is as follows: B Version: –40
°
C to +85
°
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
1
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