- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄2065 > ADG3304BRUZ-REEL (Analog Devices Inc)IC XLATOR 4CH 1.2/5.5V 14TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADG3304BRUZ-REEL |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC XLATOR 4CH 1.2/5.5V 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 4 |
| 輸入類(lèi)型： | 邏輯 |
| 輸出類(lèi)型： | 邏輯 |
| 數(shù)據(jù)速率： | 50Mbps |
| 通道數(shù)： | 4 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
ADG3304
Data Sheet
Rev. D | Page 16 of 20
THEORY OF OPERATION
The ADG3304 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pins, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pins. Similarly, because the device is capable of
bidirectional translation, when driving the Y pins, the VCCY-
compatible logic levels are translated to VCCA-compatible logic
levels available at the A pins. When EN = 0, Pin A1 to Pin A4
and Pin Y1 to Pin Y4 are three-stated. When EN is driven high,
the ADG3304 goes into normal operation mode and performs
level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 39 shows a
simplified block diagram of a bidirectional channel.
ONE-SHOT GENERATOR
6k
6k
Y
VCCA
VCCY
T2
T1
T3
T4
A
04860-053
P
N
U1
U2
U4
U3
Figure 39. Simplified Block Diagram of an ADG3304 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using Inverter U3
and Inverter U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS
transistors (T1 to T2) for a rising edge, or the NMOS transistors
(T3 to T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in faster rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 and a
minimum peak current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3304 level translator is designed to drive CMOS-
compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.
ENABLE OPERATION
The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable pin (EN), as shown in Table 5.
Table 5. Truth Table
EN
Y I/O Pins
A I/O Pins
0
Hi-Z1
1
Normal operation2
Normal operation2
1
High impedance state.
2
In normal operation, the ADG3304 performs level translation.
While EN = 0, the ADG3304 enters into three-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input pin
can be driven with either VCCA-compatible or V-compatible
logic levels.
POWER SUPPLIES
For proper operation of the ADG3304, the voltage applied to
the VCCA must be less than or equal to the voltage applied to VCCY.
To meet this condition, the recommended power-up sequence
is VCCY first and then VCCA. The ADG3304 operates properly
only after both supply voltages reach their nominal values. It is
not recommended to use the part in a system where, during
power-up, VCCA can be greater than VCCY due to a significant
increase in the current taken from the VCCA supply. For
optimum performance, the VCCA pin and VCCY pin should be
decoupled to GND as close as possible to the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADG3308BRUZ-REEL7 | IC XLATOR 8CH 1.2-5.5V 20TSSOP |
| ADL5304ACPZ-RL | IC AMP LOG CONV 32LFCSP |
| ADL5310ACP-R2 | IC LOGARITHMIC CONV DUAL 24LFCSP |
| ADN3000-06-50A-PT | IC AMP TRANSIMPEDANCE DIEFORM |
| ADN4670BSTZ | IC CLOCK BUFFER MUX 2:10 32LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADG3304BRUZ-REEL7 | 功能描述:IC XLATR BIDIR V-LVL 4CH 14TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:100ELT 邏輯功能:變換器 位數(shù):1 輸入類(lèi)型:TTL 輸出類(lèi)型:差分 數(shù)據(jù)速率:- 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無(wú)/是 傳輸延遲（最大）:0.6ns 電源電壓:3 V ~ 3.8 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:Digi-Reel® 產(chǎn)品目錄頁(yè)面:1088 (CN2011-ZH PDF) 其它名稱(chēng):576-1360-6 |
| ADG3304SRU-EP-RL7 | 功能描述:轉(zhuǎn)換 - 電壓電平 1.2 V - 5.5 V 4-channel BI-DIR TRANS IC RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| ADG3304SRUZ-EP-RL7 | 功能描述:IC XLATR BIDIR 1.15-5.5V 14TSSOP 制造商:analog devices inc. 系列:- 零件狀態(tài):在售 轉(zhuǎn)換器類(lèi)型:電壓電平 通道類(lèi)型:雙向 電路數(shù):1 每個(gè)電路的通道數(shù):4 電壓 - VCCA:1.15V ~ 5.5V 電壓?- VCCB:1.65V ~ 5.5V 輸入信號(hào):- 輸出信號(hào):- 輸出類(lèi)型:三態(tài)，非反相 數(shù)據(jù)速率:50Mbps 工作溫度:-55°C ~ 125°C（TA） 特性:- 安裝類(lèi)型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:14-TSSOP 標(biāo)準(zhǔn)包裝:1,000 |
| ADG3304WBRUZ-REEL | 制造商:Analog Devices 功能描述: |
| ADG3308 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Low Voltage 1.2 V to 5.5 V, Bidirectional, Logic Level Translators |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。