參數資料
| 型號： | ADF4360-0BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 扇出配送，整數-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.725GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
ADF4360-0
Data Sheet
Rev. C | Page 14 of 24
Table 8. N Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
RSV
CONTROL
BITS
5-BIT A COUNTER
13-BIT B COUNTER
DB21
DB22
DB23
CP
GAIN
DIVIDE-BY-
2
SELECT
DIVIDE-
BY-2
RESERVED
CPG
DIV2
DIVSEL
THIS BIT IS NOT USED
BY THE DEVICE AND
IS A DON'T CARE BIT.
A5
A4
..........
A2
A1
A COUNTER
DIVIDE RATIO
0
..........
0
..........
0
1
0
..........
1
0
2
0
..........
1
3
.
..........
.
..........
.
..........
.
1
..........
0
28
1
..........
0
1
29
1
..........
1
0
30
1
..........
1
31
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
OPERATION
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
0
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
1
0
N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N
× F
REF), AT THE OUTPUT, NMIN IS (P
2–P).
B13
B12
B11
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
NOT ALLOWED
..........
0
1
NOT ALLOWED
..........
0
1
0
NOT ALLOWED
..........
1
3
..........
.
..........
.
..........
.
..........
1
0
8188
..........
1
0
1
8189
..........
1
0
8190
..........
1
8191
04644-018
DIV2
0
1
DIVIDE-BY-2
FUNDAMENTAL OUTPUT
DIVIDE-BY-2
DIVSEL
0
1
DIVIDE-BY-2 SELECT (PRESCALER INPUT)
FUNDAMENTAL OUTPUT SELECTED
DIVIDE-BY-2 SELECTED
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