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參數(shù)資料
| 型號： | ADF4351BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
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Data Sheet
ADF4351
Rev. 0 | Page 13 of 28
The R counter output is used as the clock for the band select
logic. A programmable divider is provided at the R counter
output to allow division by an integer from 1 to 255; the divider
value is set using Bits[DB19:DB12] in Register 4 (R4). When the
required PFD frequency is higher than 125 kHz, the divide ratio
should be set to allow enough time for correct band selection.
Band selection takes 10 cycles of the PFD frequency, equal to
80 s. If faster lock times are required, Bit DB23 in Register 3
(R3) must be set to 1. This setting allows the user to select a
higher band select clock frequency of up to 500 kHz, which
speeds up the minimum band select time to 20 s. For phase
adjustments and small (<1 MHz) frequency adjustments, the
user can disable VCO band selection by setting Bit DB28 in
Register 1 (R1) to 1. This setting selects the phase adjust feature.
After band selection, normal PLL action resumes. The nominal
value of KV is 40 MHz/V when the N divider is driven from the
VCO output or from this value divided by D. D is the output
divider value if the N divider is driven from the RF divider output
(selected by programming Bits[DB22:DB20] in Register 4). The
ADF4351 contains linearization circuitry to minimize any vari-
ation of the product of ICP and KV to keep the loop bandwidth
constant.
The VCO shows variation of KV as the VTUNE varies within the
band and from band to band. For wideband applications cover-
ing a wide frequency range (and changing output dividers), a
value of 40 MHz/V provides the most accurate KV because this
value is closest to an average value. Figure 21 shows how KV
varies with fundamental VCO frequency, along with an average
value for the frequency band. Users may prefer this figure when
using narrow-band designs.
80
70
60
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
VC
O
SEN
SI
T
IVI
T
Y
(MH
z/
V)
FREQUENCY (GHz)
09800-
121
Figure 21. VCO Sensitivity (KV) vs. Frequency
OUTPUT STAGE
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 22.
VCO
RFOUTA+
RFOUTA–
BUFFER/
DIVIDE-BY-1/-2/-4/-8/
-16/-32/-64
09800-
010
Figure 22. Output Stage
To allow the user to optimize the power dissipation vs. the
output power requirements, the tail current of the differential
pair is programmable using Bits[DB4:DB3] in Register 4 (R4).
Four current levels can be set. These levels give output power
levels of 4 dBm, 1 dBm, +2 dBm, and +5 dBm, using a 50
resistor to AVDD and ac coupling into a 50 load. Alternatively,
both outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VVCO. The unused complementary
output must be terminated with a similar circuit to the used output.
An auxiliary output stage exists on the RFOUTB+ and RFOUTB
pins, providing a second set of differential outputs that can be
used to drive another circuit. The auxiliary output stage can be
used only if the primary outputs are enabled. If the auxiliary
output stage is not used, it can be powered down.
Another feature of the ADF4351 is that the supply current to
the RF output stage can be shut down until the part achieves
lock, as measured by the digital lock detect circuitry. This
feature is enabled by setting the mute till lock detect (MTLD)
bit in Register 4 (R4).
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| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4351BCPZ-U5 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4351BCPZ-U6 | 制造商:Analog Devices 功能描述:WIDEBAND SYNTHESIZER WITH INTEGRATED VCO - Rail/Tube |
| ADF4355-2BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4355-2BCPZ-RL7 | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1,500 |
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