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參數(shù)資料
| 型號： | ADF4351BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
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ADF4351
Data Sheet
Rev. 0 | Page 20 of 28
Charge Cancelation
Setting the DB21 bit to 1 enables charge pump charge cancel-
ation. This has the effect of reducing PFD spurs in integer-N
mode. In fractional-N mode, this bit should be set to 0.
CSR Enable
Setting the DB18 bit to 1 enables cycle slip reduction. CSR is
a method for improving lock times. Note that the signal at the
phase frequency detector (PFD) must have a 50% duty cycle for
cycle slip reduction to work. The charge pump current setting
must also be set to a minimum. For more information, see the
Clock Divider Mode
Bits[DB16:DB15] must be set to 10 to activate phase resync
(see the Phase Resync section). These bits must be set to 01
to activate fast lock (see the Fast Lock Timer and Register
Sequences section). Setting Bits[DB16:DB15] to 00 disables
the clock divider (see Figure 27).
12-Bit Clock Divider Value
Bits[DB14:DB3] set the 12-bit clock divider value. This value
is the timeout counter for activation of phase resync (see the
Phase Resync section). The clock divider value also sets the
timeout counter for fast lock (see the Fast Lock Timer and
Register Sequences section).
REGISTER 4
Control Bits
When Bits[C3:C1] are set to 100, Register 4 is programmed.
Figure 28 shows the input data format for programming this
register.
Feedback Select
The DB23 bit selects the feedback from the VCO output to the
N counter. When this bit is set to 1, the signal is taken directly
from the VCO. When this bit is set to 0, the signal is taken from
the output of the output dividers. The dividers enable coverage
of the wide frequency band (34.375 MHz to 4.4 GHz). When
the dividers are enabled and the feedback signal is taken from
the output, the RF output signals of two separately configured
PLLs are in phase. This is useful in some applications where the
positive interference of signals is required to increase the power.
RF Divider Select
Bits[DB22:DB20] select the value of the RF output divider (see
Band Select Clock Divider Value
Bits[DB19:DB12] set a divider for the band select logic clock input.
By default, the output of the R counter is the value used to clock
the band select logic, but, if this value is too high (>125 kHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Figure 28).
VCO Power-Down
Setting the DB11 bit to 0 powers the VCO up; setting this bit to 1
powers the VCO down.
Mute Till Lock Detect (MTLD)
When the DB10 bit is set to 1, the supply current to the RF output
stage is shut down until the part achieves lock, as measured by
the digital lock detect circuitry.
AUX Output Select
The DB9 bit sets the auxiliary RF output. If DB9 is set to 0, the
auxiliary RF output is the output of the RF dividers; if DB9 is set
to 1, the auxiliary RF output is the fundamental VCO frequency.
AUX Output Enable
The DB8 bit enables or disables the auxiliary RF output. If DB8
is set to 0, the auxiliary RF output is disabled; if DB8 is set to 1,
the auxiliary RF output is enabled.
AUX Output Power
Bits[DB7:DB6] set the value of the auxiliary RF output power
level (see Figure 28).
RF Output Enable
The DB5 bit enables or disables the primary RF output. If DB5
is set to 0, the primary RF output is disabled; if DB5 is set to 1,
the primary RF output is enabled.
Output Power
Bits[DB4:DB3] set the value of the primary RF output power
level (see Figure 28).
REGISTER 5
Control Bits
When Bits[C3:C1] are set to 101, Register 5 is programmed.
Figure 29 shows the input data format for programming this
register.
Lock Detect Pin Operation
Bits[DB23:DB22] set the operation of the lock detect (LD) pin
(see Figure 29).
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF4351 registers should be started in the
following sequence:
1. Register 5
2. Register 4
3. Register 3
4. Register 2
5. Register 1
6. Register 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4351BCPZ-U5 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4351BCPZ-U6 | 制造商:Analog Devices 功能描述:WIDEBAND SYNTHESIZER WITH INTEGRATED VCO - Rail/Tube |
| ADF4355-2BCPZ | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4355-2BCPZ-RL7 | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1,500 |
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